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board_f: Drop return value from initdram()
[oweals/u-boot.git] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr2.c
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index d30f442eb387cb765f4006eddaccd4c890fc50a8..87fd5e65e0210cdbce4b5f5e4cf46629b8b5bf91 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -33,6 +33,8 @@
 
 #include "ecc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                                \
        do {                                                            \
                u32 data;                                               \
@@ -49,7 +51,6 @@
                       "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
        } while (0)
 
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 static void update_rdcc(void)
 {
        u32 val;
@@ -72,7 +73,6 @@ static void update_rdcc(void)
                }
        }
 }
-#endif
 
 #if defined(CONFIG_440)
 /*
@@ -101,7 +101,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);
 
 #define MULDIV64(m1, m2, d)    (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 
-#if !defined(CONFIG_NAND_SPL)
 /*-----------------------------------------------------------------------------+
  * sdram_memsize
  *-----------------------------------------------------------------------------*/
@@ -217,7 +216,6 @@ void board_add_ram_info(int use_default)
        val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
        printf(", CL%d)", val);
 }
-#endif /* !CONFIG_NAND_SPL */
 
 #if defined(CONFIG_SPD_EEPROM)
 
@@ -418,7 +416,7 @@ static unsigned char spd_read(uchar chip, uint addr)
  *              banks appropriately. If Auto Memory Configuration is
  *              not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int initdram(void)
 {
        unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
        unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -428,6 +426,16 @@ phys_size_t initdram(int board_type)
        int write_recovery;
        phys_size_t dram_size = 0;
 
+       if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) {
+               /*
+                * Reduce RAM size to avoid overwriting memory used by
+                * current stack? Not sure what is happening.
+                */
+               gd->ram_size = sdram_memsize() / 2;
+
+               return 0;
+       }
+
        num_dimm_banks = sizeof(iic0_dimm_addr);
 
        /*------------------------------------------------------------------
@@ -442,8 +450,7 @@ phys_size_t initdram(int board_type)
         */
 
        /* switch to correct I2C bus */
-       I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 
        /*------------------------------------------------------------------
         * Clear out the serial presence detect buffers.
@@ -647,7 +654,9 @@ phys_size_t initdram(int board_type)
         */
        set_mcsr(get_mcsr());
 
-       return sdram_memsize();
+       gd->ram_size = sdram_memsize();
+
+       return 0;
 }
 
 static void get_spd_info(unsigned long *dimm_populated,
@@ -1666,7 +1675,7 @@ static void program_mode(unsigned long *dimm_populated,
                for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
                        /* If a dimm is installed in a particular slot ... */
                        if (dimm_populated[dimm_num] != SDRAM_NONE)
-                               t_wr_ns = max(t_wr_ns,
+                               t_wr_ns = max(t_wr_ns, (unsigned long)
                                              spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
                }
 
@@ -1843,12 +1852,18 @@ static void program_tr(unsigned long *dimm_populated,
                        else
                                sdram_ddr1 = false;
 
-                       t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
-                       t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
-                       t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
-                       t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
-                       t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
-                       t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
+                       t_rcd_ns = max(t_rcd_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
+                       t_rrd_ns = max(t_rrd_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
+                       t_rp_ns  = max(t_rp_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
+                       t_ras_ns = max(t_ras_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30));
+                       t_rc_ns  = max(t_rc_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41));
+                       t_rfc_ns = max(t_rfc_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42));
                }
        }
 
@@ -1921,9 +1936,12 @@ static void program_tr(unsigned long *dimm_populated,
                for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
                        /* If a dimm is installed in a particular slot ... */
                        if (dimm_populated[dimm_num] != SDRAM_NONE) {
-                               t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
-                               t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
-                               t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
+                               t_wpc_ns = max(t_wtr_ns,
+                                              (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
+                               t_wtr_ns = max(t_wtr_ns,
+                                              (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
+                               t_rpc_ns = max(t_rpc_ns,
+                                              (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
                        }
                }
 
@@ -2319,7 +2337,8 @@ static void program_ecc(unsigned long *dimm_populated,
        for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
                /* If a dimm is installed in a particular slot ... */
                if (dimm_populated[dimm_num] != SDRAM_NONE)
-                       ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
+                       ecc = max(ecc,
+                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11));
        }
        if (ecc == 0)
                return;
@@ -2842,18 +2861,8 @@ static void test(void)
  *             time parameters.
  *             Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+int initdram(void)
 {
-       /*
-        * Only run this SDRAM init code once. For NAND booting
-        * targets like Kilauea, we call initdram() early from the
-        * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
-        * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
-        * which calls initdram() again. This time the controller
-        * mustn't be reconfigured again since we're already running
-        * from SDRAM.
-        */
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
        unsigned long val;
 
 #if defined(CONFIG_440)
@@ -2970,12 +2979,10 @@ phys_size_t initdram(int board_type)
 #endif
 
 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
        /*------------------------------------------------------------------
         | DQS calibration.
         +-----------------------------------------------------------------*/
        DQS_autocalibration();
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
        /*
@@ -3010,13 +3017,12 @@ phys_size_t initdram(int board_type)
        set_mcsr(get_mcsr());
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
-#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+       gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
 
-       return (CONFIG_SYS_MBYTES_SDRAM << 20);
+       return 0;
 }
 #endif /* CONFIG_SPD_EEPROM */
 
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #if defined(CONFIG_440)
 u32 mfdcr_any(u32 dcr)
 {
@@ -3063,7 +3069,6 @@ void mtdcr_any(u32 dcr, u32 val)
        }
 }
 #endif /* defined(CONFIG_440) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
 
 inline void ppc4xx_ibm_ddr2_register_dump(void)
 {
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