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powerpc/mpc85xx: Add board support for ucp1020
[oweals/u-boot.git] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr2.c
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index a66973ee77bc009a947792175967e8b283ac1ef1..7202c3fc46f96d94d091f0ba586b6a2b8e84ee0a 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -14,24 +14,7 @@
  *
  * COPYRIGHT   AMCC   CORPORATION 2004
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* define DEBUG for debugging output (obviously ;-)) */
@@ -66,7 +49,6 @@
                       "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
        } while (0)
 
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 static void update_rdcc(void)
 {
        u32 val;
@@ -89,7 +71,6 @@ static void update_rdcc(void)
                }
        }
 }
-#endif
 
 #if defined(CONFIG_440)
 /*
@@ -118,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);
 
 #define MULDIV64(m1, m2, d)    (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 
-#if !defined(CONFIG_NAND_SPL)
 /*-----------------------------------------------------------------------------+
  * sdram_memsize
  *-----------------------------------------------------------------------------*/
@@ -234,7 +214,6 @@ void board_add_ram_info(int use_default)
        val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
        printf(", CL%d)", val);
 }
-#endif /* !CONFIG_NAND_SPL */
 
 #if defined(CONFIG_SPD_EEPROM)
 
@@ -445,6 +424,14 @@ phys_size_t initdram(int board_type)
        int write_recovery;
        phys_size_t dram_size = 0;
 
+       if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) {
+               /*
+                * Reduce RAM size to avoid overwriting memory used by
+                * current stack? Not sure what is happening.
+                */
+               return sdram_memsize() / 2;
+       }
+
        num_dimm_banks = sizeof(iic0_dimm_addr);
 
        /*------------------------------------------------------------------
@@ -1682,7 +1669,7 @@ static void program_mode(unsigned long *dimm_populated,
                for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
                        /* If a dimm is installed in a particular slot ... */
                        if (dimm_populated[dimm_num] != SDRAM_NONE)
-                               t_wr_ns = max(t_wr_ns,
+                               t_wr_ns = max(t_wr_ns, (unsigned long)
                                              spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
                }
 
@@ -1859,12 +1846,18 @@ static void program_tr(unsigned long *dimm_populated,
                        else
                                sdram_ddr1 = false;
 
-                       t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
-                       t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
-                       t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
-                       t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
-                       t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
-                       t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
+                       t_rcd_ns = max(t_rcd_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
+                       t_rrd_ns = max(t_rrd_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
+                       t_rp_ns  = max(t_rp_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
+                       t_ras_ns = max(t_ras_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30));
+                       t_rc_ns  = max(t_rc_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41));
+                       t_rfc_ns = max(t_rfc_ns,
+                                      (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42));
                }
        }
 
@@ -1937,9 +1930,12 @@ static void program_tr(unsigned long *dimm_populated,
                for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
                        /* If a dimm is installed in a particular slot ... */
                        if (dimm_populated[dimm_num] != SDRAM_NONE) {
-                               t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
-                               t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
-                               t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
+                               t_wpc_ns = max(t_wtr_ns,
+                                              (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
+                               t_wtr_ns = max(t_wtr_ns,
+                                              (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
+                               t_rpc_ns = max(t_rpc_ns,
+                                              (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
                        }
                }
 
@@ -2335,7 +2331,8 @@ static void program_ecc(unsigned long *dimm_populated,
        for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
                /* If a dimm is installed in a particular slot ... */
                if (dimm_populated[dimm_num] != SDRAM_NONE)
-                       ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
+                       ecc = max(ecc,
+                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11));
        }
        if (ecc == 0)
                return;
@@ -2860,16 +2857,6 @@ static void test(void)
  *---------------------------------------------------------------------------*/
 phys_size_t initdram(int board_type)
 {
-       /*
-        * Only run this SDRAM init code once. For NAND booting
-        * targets like Kilauea, we call initdram() early from the
-        * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
-        * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
-        * which calls initdram() again. This time the controller
-        * mustn't be reconfigured again since we're already running
-        * from SDRAM.
-        */
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
        unsigned long val;
 
 #if defined(CONFIG_440)
@@ -2986,12 +2973,10 @@ phys_size_t initdram(int board_type)
 #endif
 
 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
        /*------------------------------------------------------------------
         | DQS calibration.
         +-----------------------------------------------------------------*/
        DQS_autocalibration();
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
        /*
@@ -3026,13 +3011,10 @@ phys_size_t initdram(int board_type)
        set_mcsr(get_mcsr());
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
-#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-
        return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
 #endif /* CONFIG_SPD_EEPROM */
 
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #if defined(CONFIG_440)
 u32 mfdcr_any(u32 dcr)
 {
@@ -3079,7 +3061,6 @@ void mtdcr_any(u32 dcr, u32 val)
        }
 }
 #endif /* defined(CONFIG_440) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
 
 inline void ppc4xx_ibm_ddr2_register_dump(void)
 {
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