Merge branch 'master' of git://git.denx.de/u-boot-nios
[oweals/u-boot.git] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr.c
index ec7291f9c8fe987b1cea21d5d4a567f7595aca67..8a20a2b1e05befac0092c549e500ab141f2983d1 100644 (file)
@@ -380,8 +380,6 @@ static void program_cfg0(unsigned long *dimm_populated,
        unsigned char ecc;
        unsigned char attributes;
        unsigned long data_width;
-       unsigned long dimm_32bit;
-       unsigned long dimm_64bit;
 
        /*
         * get Memory Controller Options 0 data
@@ -423,10 +421,8 @@ static void program_cfg0(unsigned long *dimm_populated,
                                (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
                                (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
                        if (data_width == 64 || data_width == 72) {
-                               dimm_64bit = TRUE;
                                cfg0 |= SDRAM_CFG0_DMWD_64;
                        } else if (data_width == 32 || data_width == 40) {
-                               dimm_32bit = TRUE;
                                cfg0 |= SDRAM_CFG0_DMWD_32;
                        } else {
                                printf("WARNING: DIMM with datawidth of %lu bits.\n",
@@ -820,7 +816,7 @@ static void program_tr0(unsigned long *dimm_populated,
                break;
        }
 
-       debug("tr0: %x\n", tr0);
+       debug("tr0: %lx\n", tr0);
        mtsdram(SDRAM0_TR0, tr0);
 }
 
@@ -1051,7 +1047,7 @@ static void program_tr1(void)
        }
        tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
 
-       debug("tr1: %x\n", tr1);
+       debug("tr1: %lx\n", tr1);
 
        /*
         * program SDRAM Timing Register 1 TR1
@@ -1124,7 +1120,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
                        num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
                        num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
                        bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
-                       debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
+                       debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num,
                              num_row_addr, num_col_addr, num_banks);
 
                        /*
@@ -1193,9 +1189,11 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
                                bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
                                        (4 << 20) * bank_size_id;
                                bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
-                               debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
-                                     dimm_num, i, ctrl_bank_num[dimm_num]+i,
-                                     bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
+                               debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
+                                       "bank_size_bytes=%ld\n",
+                                       dimm_num, i,
+                                       ctrl_bank_num[dimm_num] + i,
+                                       bank_parms[ctrl_bank_num[dimm_num] + i].bank_size_bytes);
                        }
                }
        }
@@ -1239,7 +1237,8 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
                                bank_parms[sorted_bank_num[bx_cr_num]].cr;
                        mtdcr(SDRAM0_CFGDATA, temp);
                        bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
-                       debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
+                       debug("SDRAM0_B%ldCR=0x%08lx\n",
+                               sorted_bank_num[bx_cr_num], temp);
                }
        }