reset_phy();
#endif
-#ifdef CONFIG_FADS
-#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
- /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
- *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#else
- *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#endif
-#endif
-
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
rxIdx = 0;
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
-#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
- /*
- * Port C is used to control the PHY,MC68160.
- */
- immr->im_ioport.iop_pcdir |=
- (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
-
- immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
- immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#endif /* MPC860ADS */
-
-#ifdef CONFIG_RPXCLASSIC
- *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
- *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
-#endif
-
-#ifdef CONFIG_RPXLITE
- *((uchar *) BCSR0) |= BCSR0_ETHEN;
-#endif
-
-#if defined(CONFIG_QS860T)
- /*
- * PB27=FDE-, set output low for full duplex
- * PB26=Link Test Enable, normally high output
- */
- immr->im_cpm.cp_pbdir |= 0x00000030;
- immr->im_cpm.cp_pbdat |= 0x00000020;
- immr->im_cpm.cp_pbdat &= ~0x00000010;
-#endif /* QS860T */
-
-#ifdef CONFIG_MBX
- board_ether_init ();
-#endif
-
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
- /*
- * Work around transmit problem with first eth packet
- */
-#if defined (CONFIG_FADS)
- udelay (10000); /* wait 10 ms */
-#elif defined(CONFIG_RPXCLASSIC)
- udelay (100000); /* wait 100 ms */
-#endif
-
return 1;
}