+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
#endif
mtspr HID0,r0
-#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
mtspr DBCR0,r0
#endif
-#ifdef CONFIG_MPC8569
+#ifdef CONFIG_ARCH_MPC8569
#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
tlbivax 0,r4
isync
-#endif /* CONFIG_MPC8569 */
+#endif /* CONFIG_ARCH_MPC8569 */
/*
* Search for the TLB that covers the code we're executing, and shrink it
ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
sync
stw r4, 0(r3) /* invalidate L2 */
+ /* Poll till the bits are cleared */
1: sync
lwz r0, 0(r3)
twi 0, r0, 0
isync
and. r1, r0, r4
bne 1b
+
+ /* L2PE must be set before L2 cache is enabled */
+ lis r4, (L2CSR0_L2PE)@h
+ ori r4, r4, (L2CSR0_L2PE)@l
+ sync
+ stw r4, 0(r3) /* enable L2 parity/ECC error checking */
+ /* Poll till the bit is set */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ beq 1b
+
lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
ori r4, r4, (L2CSR0_L2REP_MODE)@l
sync
stw r4, 0(r3) /* enable L2 */
+ /* Poll till the bit is set */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ beq 1b
+
delete_ccsr_l2_tlb:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
#endif
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
/* create a temp mapping in AS = 1 for Flash mapping
* created by PBL for ISBC code
- */
+ */
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
-#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT)
+/*
+ * For Targets without CONFIG_SPL like P3, P5
+ * and for targets with CONFIG_SPL like T1, T2, T4, only for
+ * u-boot-spl i.e. CONFIG_SPL_BUILD
+ */
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \
+ (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
* to L3 Address configured by PBL for ISBC code
- */
+ */
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
li r0,0
1:
dcbz r0,r3
- dcbtls 0,r0,r3
+#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
+ dcbtls 2, r0, r3
+ dcbtls 0, r0, r3
+#else
+ dcbtls 0, r0, r3
+#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+ /* Leave 16+ byte for back chain termination and NULL return address */
+ subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
+#endif
+
+ /* End of RAM */
+ lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+ li r0,0
+
+1: subi r4,r4,4
+ stw r0,0(r4)
+ cmplw r4,r3
+ bne 1b
+
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+ addi r3,r3,16 /* Pre-relocation malloc area */
+ stw r3,GD_MALLOC_BASE(r4)
+ subi r3,r3,16
+#endif
li r0,0
stw r0,0(r3) /* Terminate Back Chain */
stw r0,+4(r3) /* NULL return address. */
mr r1,r3 /* Transfer to SP(r1) */
GET_GOT
+ /* Needed for -msingle-pic-base */
+ bl _GLOBAL_OFFSET_TABLE_@local-4
+ mflr r30
/* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
mr r3, r24
mtlr r8
isync
mfspr r4,L1CSR1
- ori r4,r4,0x0001
- oris r4,r4,0x0001
+ ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
+ oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
mtspr L1CSR1,r4
isync
blr
mtlr r8
isync
mfspr r0,L1CSR0
- ori r0,r0,0x0001
- oris r0,r0,0x0001
+ ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
+ oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
msync
isync
mtspr L1CSR0,r0
andi. r3,r3,L1CSR0_DCE
blr
- .globl get_pvr
-get_pvr:
- mfspr r3,PVR
- blr
-
- .globl get_svr
-get_svr:
- mfspr r3,SVR
- blr
-
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
+#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
+ dcblc 2, r0, r3
+ dcblc 0, r0, r3
+#else
dcblc r0,r3
+#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync
projects / oweals / u-boot.git / blobdiff