CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
+
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT)
+ /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+ * to L3 Address configured by PBL for ISBC code
+ */
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
li r0,0
1:
dcbz r0,r3
- dcbtls 0,r0,r3
+#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */
+ dcbtls 2, r0, r3
+#else
+ dcbtls 0, r0, r3
+#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
/* No FPU on MPC85xx. This exception is not supposed to happen.
*/
STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
-
-/*
- * r0 - SYSCALL number
- * r3-... arguments
- */
-SystemCall:
- addis r11,r0,0 /* get functions table addr */
- ori r11,r11,0 /* Note: this code is patched in trap_init */
- addis r12,r0,0 /* get number of functions */
- ori r12,r12,0
-
- cmplw 0,r0,r12
- bge 1f
-
- rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
- add r11,r11,r0
- lwz r11,0(r11)
-
- li r20,0xd00-4 /* Get stack pointer */
- lwz r12,0(r20)
- subi r12,r12,12 /* Adjust stack pointer */
- li r0,0xc00+_end_back-SystemCall
- cmplw 0,r0,r12 /* Check stack overflow */
- bgt 1f
- stw r12,0(r20)
-
- mflr r0
- stw r0,0(r12)
- mfspr r0,SRR0
- stw r0,4(r12)
- mfspr r0,SRR1
- stw r0,8(r12)
-
- li r12,0xc00+_back-SystemCall
- mtlr r12
- mtspr SRR0,r11
-
-1: SYNC
- rfi
-_back:
-
- mfmsr r11 /* Disable interrupts */
- li r12,0
- ori r12,r12,MSR_EE
- andc r11,r11,r12
- SYNC /* Some chip revs need this... */
- mtmsr r11
- SYNC
-
- li r12,0xd00-4 /* restore regs */
- lwz r12,0(r12)
-
- lwz r11,0(r12)
- mtlr r11
- lwz r11,4(r12)
- mtspr SRR0,r11
- lwz r11,8(r12)
- mtspr SRR1,r11
-
- addi r12,r12,12 /* Adjust stack pointer */
- li r20,0xd00-4
- stw r12,0(r20)
-
- SYNC
- rfi
-_end_back:
-
+ STD_EXCEPTION(0x0900, SystemCall, UnknownException)
STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
SYNC
rfi
-crit_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SPRN_CSRR0,r2
- mtspr SPRN_CSRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfci
-
-mck_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SPRN_MCSRR0,r2
- mtspr SPRN_MCSRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfmci
-
/* Cache functions.
*/
.globl flush_icache
andi. r3,r3,L1CSR0_DCE
blr
- .globl get_pir
-get_pir:
- mfspr r3,PIR
- blr
-
.globl get_pvr
get_pvr:
mfspr r3,PVR
mfspr r3,SVR
blr
- .globl wr_tcr
-wr_tcr:
- mtspr TCR,r3
- blr
-
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
*/
.globl trap_init
trap_init:
+ mflr r11
+ bl _GLOBAL_OFFSET_TABLE_-4
+ mflr r12
+
/* Update IVORs as per relocation */
mtspr IVPR,r3
- li r4,CriticalInput@l
+ lwz r4,CriticalInput@got(r12)
mtspr IVOR0,r4 /* 0: Critical input */
- li r4,MachineCheck@l
+ lwz r4,MachineCheck@got(r12)
mtspr IVOR1,r4 /* 1: Machine check */
- li r4,DataStorage@l
+ lwz r4,DataStorage@got(r12)
mtspr IVOR2,r4 /* 2: Data storage */
- li r4,InstStorage@l
+ lwz r4,InstStorage@got(r12)
mtspr IVOR3,r4 /* 3: Instruction storage */
- li r4,ExtInterrupt@l
+ lwz r4,ExtInterrupt@got(r12)
mtspr IVOR4,r4 /* 4: External interrupt */
- li r4,Alignment@l
+ lwz r4,Alignment@got(r12)
mtspr IVOR5,r4 /* 5: Alignment */
- li r4,ProgramCheck@l
+ lwz r4,ProgramCheck@got(r12)
mtspr IVOR6,r4 /* 6: Program check */
- li r4,FPUnavailable@l
+ lwz r4,FPUnavailable@got(r12)
mtspr IVOR7,r4 /* 7: floating point unavailable */
- li r4,SystemCall@l
+ lwz r4,SystemCall@got(r12)
mtspr IVOR8,r4 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
- li r4,Decrementer@l
+ lwz r4,Decrementer@got(r12)
mtspr IVOR10,r4 /* 10: Decrementer */
- li r4,IntervalTimer@l
+ lwz r4,IntervalTimer@got(r12)
mtspr IVOR11,r4 /* 11: Interval timer */
- li r4,WatchdogTimer@l
+ lwz r4,WatchdogTimer@got(r12)
mtspr IVOR12,r4 /* 12: Watchdog timer */
- li r4,DataTLBError@l
+ lwz r4,DataTLBError@got(r12)
mtspr IVOR13,r4 /* 13: Data TLB error */
- li r4,InstructionTLBError@l
+ lwz r4,InstructionTLBError@got(r12)
mtspr IVOR14,r4 /* 14: Instruction TLB error */
- li r4,DebugBreakpoint@l
+ lwz r4,DebugBreakpoint@got(r12)
mtspr IVOR15,r4 /* 15: Debug */
+ mtlr r11
blr
.globl unlock_ram_in_cache
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
+#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */
+ dcblc 2, r0, r3
+#else
dcblc r0,r3
+#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync
projects / oweals / u-boot.git / blobdiff