Merge git://git.denx.de/u-boot-rockchip

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / start.S

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 28f04eefabb86e959e7ec113d9f10587446ab2e8..d867e2a767a4f5b91c5e70211d13dd943c136957 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1052,6 +1052,17 @@ create_init_ram_area:
                CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
                CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
                0, r6
+
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT)
+       /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+        * to L3 Address configured by PBL for ISBC code
+       */
+       create_tlb1_entry 15, \
+               1, BOOKE_PAGESZ_1M, \
+               CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+               CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+               0, r6
+
 #else
        /*
         * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
@@ -1105,7 +1116,11 @@ switch_as:
        li      r0,0
 1:
        dcbz    r0,r3
-       dcbtls  0,r0,r3
+#ifdef CONFIG_E6500    /* Lock/unlock L2 cache instead of L1 */
+       dcbtls  2, r0, r3
+#else
+       dcbtls  0, r0, r3
+#endif
        addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
        bdnz    1b
 
@@ -1664,41 +1679,46 @@ clear_bss:
         */
        .globl  trap_init
 trap_init:
+       mflr    r11
+       bl      _GLOBAL_OFFSET_TABLE_-4
+       mflr    r12
+
        /* Update IVORs as per relocation */
        mtspr   IVPR,r3
 
-       li      r4,CriticalInput@l
+       lwz     r4,CriticalInput@got(r12)
        mtspr   IVOR0,r4        /* 0: Critical input */
-       li      r4,MachineCheck@l
+       lwz     r4,MachineCheck@got(r12)
        mtspr   IVOR1,r4        /* 1: Machine check */
-       li      r4,DataStorage@l
+       lwz     r4,DataStorage@got(r12)
        mtspr   IVOR2,r4        /* 2: Data storage */
-       li      r4,InstStorage@l
+       lwz     r4,InstStorage@got(r12)
        mtspr   IVOR3,r4        /* 3: Instruction storage */
-       li      r4,ExtInterrupt@l
+       lwz     r4,ExtInterrupt@got(r12)
        mtspr   IVOR4,r4        /* 4: External interrupt */
-       li      r4,Alignment@l
+       lwz     r4,Alignment@got(r12)
        mtspr   IVOR5,r4        /* 5: Alignment */
-       li      r4,ProgramCheck@l
+       lwz     r4,ProgramCheck@got(r12)
        mtspr   IVOR6,r4        /* 6: Program check */
-       li      r4,FPUnavailable@l
+       lwz     r4,FPUnavailable@got(r12)
        mtspr   IVOR7,r4        /* 7: floating point unavailable */
-       li      r4,SystemCall@l
+       lwz     r4,SystemCall@got(r12)
        mtspr   IVOR8,r4        /* 8: System call */
        /* 9: Auxiliary processor unavailable(unsupported) */
-       li      r4,Decrementer@l
+       lwz     r4,Decrementer@got(r12)
        mtspr   IVOR10,r4       /* 10: Decrementer */
-       li      r4,IntervalTimer@l
+       lwz     r4,IntervalTimer@got(r12)
        mtspr   IVOR11,r4       /* 11: Interval timer */
-       li      r4,WatchdogTimer@l
+       lwz     r4,WatchdogTimer@got(r12)
        mtspr   IVOR12,r4       /* 12: Watchdog timer */
-       li      r4,DataTLBError@l
+       lwz     r4,DataTLBError@got(r12)
        mtspr   IVOR13,r4       /* 13: Data TLB error */
-       li      r4,InstructionTLBError@l
+       lwz     r4,InstructionTLBError@got(r12)
        mtspr   IVOR14,r4       /* 14: Instruction TLB error */
-       li      r4,DebugBreakpoint@l
+       lwz     r4,DebugBreakpoint@got(r12)
        mtspr   IVOR15,r4       /* 15: Debug */
 
+       mtlr    r11
        blr
 
 .globl unlock_ram_in_cache
@@ -1711,7 +1731,11 @@ unlock_ram_in_cache:
        slwi    r4,r4,(10 - 1 - L1_CACHE_SHIFT)
        mtctr   r4
 1:     dcbi    r0,r3
+#ifdef CONFIG_E6500    /* lock/unlock L2 cache instead of L1 */
+       dcblc   2, r0, r3
+#else
        dcblc   r0,r3
+#endif
        addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
        bdnz    1b
        sync