env: Rename getenv_hex(), getenv_yesno(), getenv_ulong()

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 2af9143683d280ca81cf26c7348c66f75960a0d0..cb8281e19e13e15204cfe6fb129149308207a342 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(sys_info_t *sys_info)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-       struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-       u32 ccr;
-#endif
 #ifdef CONFIG_FSL_CORENET
        volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
        unsigned int cpu;
@@ -130,9 +126,8 @@ void get_sys_info(sys_info_t *sys_info)
         * it uses 6.
         * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
         */
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
-       defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
-       defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
+       defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
        svr = get_svr();
        switch (SVR_SOC_VER(svr)) {
        case SVR_T4240:
@@ -202,11 +197,11 @@ void get_sys_info(sys_info_t *sys_info)
        }
 #endif
 
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
-       defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
+       defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 #define FM1_CLK_SEL    0xe0000000
 #define FM1_CLK_SHIFT  29
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 #define FM1_CLK_SEL    0x00000007
 #define FM1_CLK_SHIFT  0
 #else
@@ -216,7 +211,7 @@ void get_sys_info(sys_info_t *sys_info)
 #define FM1_CLK_SHIFT  26
 #endif
 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
-#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
        rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
 #else
        rcw_tmp = in_be32(&gur->rcwsr[7]);
@@ -456,7 +451,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
 #define ESDHC_CLK_SEL  0x00000007
 #define ESDHC_CLK_SHIFT        0
 #define ESDHC_CLK_RCWSR        15
@@ -480,7 +475,7 @@ void get_sys_info(sys_info_t *sys_info)
        case 4:
                sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
                break;
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
        case 5:
                sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
                break;
@@ -596,7 +591,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_QE
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
        sys_info->freq_qe =  sys_info->freq_systembus;
 #else
        qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
@@ -612,39 +607,13 @@ void get_sys_info(sys_info_t *sys_info)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
-       uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
-       /* We will program LCRR to this value later */
-       lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-       lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
-       if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
-               /* If this is corenet based SoC, bit-representation
-                * for four times the clock divider values.
-                */
-               lcrr_div *= 4;
-#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-       !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
-               /*
-                * Yes, the entire PQ38 family use the same
-                * bit-representation for twice the clock divider values.
-                */
-               lcrr_div *= 2;
-#endif
-               sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
-       } else {
-               /* In case anyone cares what the unknown value is */
-               sys_info->freq_localbus = lcrr_div;
-       }
+       sys_info->freq_localbus = sys_info->freq_systembus /
+                                               CONFIG_SYS_FSL_LBC_CLK_DIV;
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-       ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-       ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-       sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+       sys_info->freq_localbus = sys_info->freq_systembus /
+                                               CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
 
@@ -707,8 +676,7 @@ int get_clocks (void)
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
        gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
 #else
-#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) ||\
-       defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
        gd->arch.sdhc_clk = gd->bus_clk;
 #else
        gd->arch.sdhc_clk = gd->bus_clk / 2;