Merge branch 'master' of git://git.denx.de/u-boot-arm into master

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 46ae80c4d819b244de758d60a28a09cd6095d4a5..adf09efa2795aa4f0934ddf4d0439938c07a46b1 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -74,12 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
        uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
        unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
        uint mem_pll_rat;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+       uint single_src;
+#endif
 
        sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+       /*
+        * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
+        * are driven by separate DDR Refclock or single source
+        * differential clock.
+        */
+       single_src = (in_be32(&gur->rcwsr[5]) >>
+                     FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
+                     FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
+       /*
+        * For single source clocking, both ddrclock and syclock
+        * are driven by differential sysclock.
+        */
+       if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
+               printf("Single Source Clock Configuration\n");
+               sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+       } else
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
-       sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+               sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
-       sys_info->freq_ddrbus = sysclk;
+               sys_info->freq_ddrbus = sysclk;
 #endif
 
        sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
@@ -130,7 +151,8 @@ void get_sys_info(sys_info_t *sys_info)
                sys_info->freq_processor[cpu] =
                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
        }
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
+       defined(CONFIG_PPC_T2081)
 #define FM1_CLK_SEL    0xe0000000
 #define FM1_CLK_SHIFT  29
 #else
@@ -229,6 +251,9 @@ void get_sys_info(sys_info_t *sys_info)
        case 4:
                sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
                break;
+       case 5:
+               sys_info->freq_fman[1] = sys_info->freq_systembus;
+               break;
        case 6:
                sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
                break;