Merge tag 'u-boot-rockchip-20191124' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / mpc8572_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
index 3632eb557e4e7385ac7bce20a0f10a4f5b8629e9..0e0c63a14f325621d16bd92be08c913f4d011505 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
@@ -28,6 +27,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
 
 int is_serdes_configured(enum srds_prtcl prtcl)
 {
+       if (!(serdes1_prtcl_map & (1 << NONE)))
+               fsl_serdes_init();
+
        return (1 << prtcl) & serdes1_prtcl_map;
 }
 
@@ -39,6 +41,9 @@ void fsl_serdes_init(void)
                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;
        int lane;
 
+       if (serdes1_prtcl_map & (1 << NONE))
+               return;
+
        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
        if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
@@ -62,4 +67,7 @@ void fsl_serdes_init(void)
 
        if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
                serdes1_prtcl_map |= (1 << SGMII_TSEC4);
+
+       /* Set the first bit to indicate serdes has been initialized */
+       serdes1_prtcl_map |= (1 << NONE);
 }