Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / fsl_corenet_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 72d5e3007d9d20fc7f6b9205976988f17b82597d..fcfa73023347c4525f1d9f1ae3ff7d55c4386bcc 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -1,10 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <env.h>
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 #include <hwconfig.h>
 #endif
@@ -76,7 +76,7 @@ static const struct {
        { 17, 163, FSL_SRDS_BANK_2 },
        { 18, 164, FSL_SRDS_BANK_2 },
        { 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
        { 20, 170, FSL_SRDS_BANK_3 },
        { 21, 171, FSL_SRDS_BANK_3 },
        { 22, 172, FSL_SRDS_BANK_3 },
@@ -491,7 +491,7 @@ void fsl_serdes_init(void)
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        int cfg;
        serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
        serdes_corenet_t *srds2_regs;
 #endif
        int lane, bank, idx;
@@ -514,7 +514,7 @@ void fsl_serdes_init(void)
         * Extract hwconfig from environment since we have not properly setup
         * the environment but need it for ddr config params
         */
-       if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+       if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
                buf = buffer;
 #endif
        if (serdes_prtcl_map & (1 << NONE))
@@ -577,7 +577,7 @@ void fsl_serdes_init(void)
                }
        }
 
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
        /*
         * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
         * protocols, these lanes are routed to SATA.  We use serdes_prtcl_map
@@ -607,6 +607,9 @@ void fsl_serdes_init(void)
 
        soc_serdes_init();
 
+       /* Set the first bit to indicate serdes has been initialized */
+       serdes_prtcl_map |= (1 << NONE);
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
        /*
         * Bank two uses the clock from bank three, so if bank two is enabled,
@@ -862,9 +865,6 @@ void fsl_serdes_init(void)
                             SRDS_RSTCTL_SDPD);
        }
 #endif
-
-       /* Set the first bit to indicate serdes has been initialized */
-       serdes_prtcl_map |= (1 << NONE);
 }
 
 const char *serdes_clock_to_string(u32 clock)