Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / fsl_corenet_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 680b5222bc419e80145aef871ec518d568170e38..f5126e2c8acfb5c2b215d8182de1d1070fab09e7 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -1,10 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <env.h>
+#include <log.h>
+#include <time.h>
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 #include <hwconfig.h>
 #endif
@@ -13,7 +15,8 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/fsl_law.h>
-#include <asm/errno.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
 #include "fsl_corenet_serdes.h"
 
 /*
@@ -76,7 +79,7 @@ static const struct {
        { 17, 163, FSL_SRDS_BANK_2 },
        { 18, 164, FSL_SRDS_BANK_2 },
        { 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
        { 20, 170, FSL_SRDS_BANK_3 },
        { 21, 171, FSL_SRDS_BANK_3 },
        { 22, 172, FSL_SRDS_BANK_3 },
@@ -136,6 +139,9 @@ int is_serdes_configured(enum srds_prtcl device)
        if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
                return 0;
 
+       if (!(serdes_prtcl_map & (1 << NONE)))
+               fsl_serdes_init();
+
        return (1 << device) & serdes_prtcl_map;
 }
 
@@ -488,7 +494,7 @@ void fsl_serdes_init(void)
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        int cfg;
        serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
        serdes_corenet_t *srds2_regs;
 #endif
        int lane, bank, idx;
@@ -511,9 +517,11 @@ void fsl_serdes_init(void)
         * Extract hwconfig from environment since we have not properly setup
         * the environment but need it for ddr config params
         */
-       if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+       if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
                buf = buffer;
 #endif
+       if (serdes_prtcl_map & (1 << NONE))
+               return;
 
        /* Is serdes enabled at all? */
        if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -572,7 +580,7 @@ void fsl_serdes_init(void)
                }
        }
 
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
        /*
         * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
         * protocols, these lanes are routed to SATA.  We use serdes_prtcl_map
@@ -602,6 +610,9 @@ void fsl_serdes_init(void)
 
        soc_serdes_init();
 
+       /* Set the first bit to indicate serdes has been initialized */
+       serdes_prtcl_map |= (1 << NONE);
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
        /*
         * Bank two uses the clock from bank three, so if bank two is enabled,
@@ -858,3 +869,20 @@ void fsl_serdes_init(void)
        }
 #endif
 }
+
+const char *serdes_clock_to_string(u32 clock)
+{
+       switch (clock) {
+       case SRDS_PLLCR0_RFCK_SEL_100:
+               return "100";
+       case SRDS_PLLCR0_RFCK_SEL_125:
+               return "125";
+       case SRDS_PLLCR0_RFCK_SEL_156_25:
+               return "156.25";
+       case SRDS_PLLCR0_RFCK_SEL_161_13:
+               return "161.1328123";
+       default:
+               return "150";
+       }
+}
+