{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
serdes_corenet_t *srds2_regs;
#endif
int lane, bank, idx;
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
- if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+ if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
#endif
if (serdes_prtcl_map & (1 << NONE))
}
}
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
/*
* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
* protocols, these lanes are routed to SATA. We use serdes_prtcl_map