/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_law.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include "fsl_corenet_serdes.h"
/*
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 22, 168, FSL_SRDS_BANK_3 },
{ 23, 169, FSL_SRDS_BANK_3 },
#endif
+#if SRDS_MAX_BANK > 3
+ { 24, 175, FSL_SRDS_BANK_4 },
+ { 25, 176, FSL_SRDS_BANK_4 },
+#endif
};
int serdes_get_lane_idx(int lane)
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return 0;
+ if (!(serdes_prtcl_map & (1 << NONE)))
+ fsl_serdes_init();
+
return (1 << device) & serdes_prtcl_map;
}
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
serdes_corenet_t *srds2_regs;
#endif
int lane, bank, idx;
size_t arglen;
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
- int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */
+ int need_serdes_a001; /* true == need work-around for SERDES A001 */
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
char buffer[HWCONFIG_BUFFER_SIZE];
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
- if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+ if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
#endif
+ if (serdes_prtcl_map & (1 << NONE))
+ return;
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
}
}
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
/*
* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
* protocols, these lanes are routed to SATA. We use serdes_prtcl_map
soc_serdes_init();
+ /* Set the first bit to indicate serdes has been initialized */
+ serdes_prtcl_map |= (1 << NONE);
+
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
/*
* Bank two uses the clock from bank three, so if bank two is enabled,
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
/*
- * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
- * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
- * AURORA before the device is initialized.
+ * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
+ * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
+ * or AURORA before the device is initialized.
+ *
+ * Note that this part of the SERDES-9 work-around is
+ * redundant if the work-around for A-4580 has already been
+ * applied via PBI.
*/
switch (lane_prtcl) {
case SGMII_FM1_DTSEC1:
case SRIO1:
case SRIO2:
case AURORA:
- clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
- SRDS_TTLCR0_FLT_SEL_MASK,
- SRDS_TTLCR0_FLT_SEL_750PPM |
- SRDS_TTLCR0_PM_DIS);
+ out_be32(&srds_regs->lane[idx].ttlcr0,
+ SRDS_TTLCR0_FLT_SEL_KFR_26 |
+ SRDS_TTLCR0_FLT_SEL_KPH_28 |
+ SRDS_TTLCR0_FLT_SEL_750PPM |
+ SRDS_TTLCR0_FREQOVD_EN);
+ break;
default:
break;
}
}
#endif
}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ case SRDS_PLLCR0_RFCK_SEL_161_13:
+ return "161.1328123";
+ default:
+ return "150";
+ }
+}
+