net: Move enetaddr env access code to env config instead of net config

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / fsl_corenet_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 20d039f3386e5682e379d4bd736bb1954bef9f0c..79d6544a09805da4267016058300278e519ce503 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -491,7 +491,7 @@ void fsl_serdes_init(void)
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        int cfg;
        serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
        serdes_corenet_t *srds2_regs;
 #endif
        int lane, bank, idx;
@@ -514,7 +514,7 @@ void fsl_serdes_init(void)
         * Extract hwconfig from environment since we have not properly setup
         * the environment but need it for ddr config params
         */
-       if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+       if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
                buf = buffer;
 #endif
        if (serdes_prtcl_map & (1 << NONE))
@@ -577,7 +577,7 @@ void fsl_serdes_init(void)
                }
        }
 
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
        /*
         * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
         * protocols, these lanes are routed to SATA.  We use serdes_prtcl_map
@@ -607,6 +607,9 @@ void fsl_serdes_init(void)
 
        soc_serdes_init();
 
+       /* Set the first bit to indicate serdes has been initialized */
+       serdes_prtcl_map |= (1 << NONE);
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
        /*
         * Bank two uses the clock from bank three, so if bank two is enabled,
@@ -862,9 +865,6 @@ void fsl_serdes_init(void)
                             SRDS_RSTCTL_SDPD);
        }
 #endif
-
-       /* Set the first bit to indicate serdes has been initialized */
-       serdes_prtcl_map |= (1 << NONE);
 }
 
 const char *serdes_clock_to_string(u32 clock)