Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / fsl_corenet2_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index de6bd11a16529d39a0580eff7b080ed12dd3a2b5..25db899e5fb806948eb4bf28ffea25bb41216095 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -13,8 +13,12 @@
 #include <asm/errno.h>
 #include "fsl_corenet2_serdes.h"
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
 static u64 serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 static u64 serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 static u64 serdes3_prtcl_map;
 #endif
@@ -78,8 +82,12 @@ int is_serdes_configured(enum srds_prtcl device)
 {
        u64 ret = 0;
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
        ret |= (1ULL << device) & serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
        ret |= (1ULL << device) & serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
        ret |= (1ULL << device) & serdes3_prtcl_map;
 #endif
@@ -97,14 +105,18 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
        int i;
 
        switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
        case FSL_SRDS_1:
                cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
                cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
                break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
        case FSL_SRDS_2:
                cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
                cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
                break;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
        case FSL_SRDS_3:
                cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
@@ -163,14 +175,18 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 void fsl_serdes_init(void)
 {
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
        serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
                CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
                FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
                FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
        serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
                CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
                FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
                FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
        serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
                CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
@@ -185,3 +201,24 @@ void fsl_serdes_init(void)
 #endif
 
 }
+
+const char *serdes_clock_to_string(u32 clock)
+{
+       switch (clock) {
+       case SRDS_PLLCR0_RFCK_SEL_100:
+               return "100";
+       case SRDS_PLLCR0_RFCK_SEL_125:
+               return "125";
+       case SRDS_PLLCR0_RFCK_SEL_156_25:
+               return "156.25";
+       case SRDS_PLLCR0_RFCK_SEL_161_13:
+               return "161.1328123";
+       default:
+#if defined(CONFIG_T4240QDS)
+               return "???";
+#else
+               return "122.88";
+#endif
+       }
+}
+