Merge branch 'master' of /home/wd/git/u-boot/master

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / fdt.c

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 1d11ab470f85c1141bfe743fe0985e7500cf0a79..8e7b827ffb9e1ed11c8a9bb343688378234d4f00 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -28,6 +28,8 @@
 #include <fdt_support.h>
 #include <asm/processor.h>
 #include <linux/ctype.h>
+#include <asm/io.h>
+#include <asm/fsl_portals.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
@@ -80,7 +82,30 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_CPC
+static inline void ft_fixup_l3cache(void *blob, int off)
+{
+       u32 line_size, num_ways, size, num_sets;
+       cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
+       u32 cfg0 = in_be32(&cpc->cpccfg0);
+
+       size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
+       num_ways = CPC_CFG0_NUM_WAYS(cfg0);
+       line_size = CPC_CFG0_LINE_SZ(cfg0);
+       num_sets = size / (line_size * num_ways);
+
+       fdt_setprop(blob, off, "cache-unified", NULL, 0);
+       fdt_setprop_cell(blob, off, "cache-block-size", line_size);
+       fdt_setprop_cell(blob, off, "cache-size", size);
+       fdt_setprop_cell(blob, off, "cache-sets", num_sets);
+       fdt_setprop_cell(blob, off, "cache-level", 3);
+#ifdef CONFIG_SYS_CACHE_STASHING
+       fdt_setprop_cell(blob, off, "cache-stash-id", 1);
+#endif
+}
+#else
 #define ft_fixup_l3cache(x, y)
+#endif
 
 #if defined(CONFIG_L2_CACHE)
 /* return size in kilobytes */
@@ -298,17 +323,17 @@ void fdt_add_enet_stashing(void *fdt)
 }
 
 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
-static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq)
+static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
+                         unsigned long freq)
 {
-       const char *path = fdt_get_alias(blob, alias);
-
-       int off = fdt_path_offset(blob, path);
+       phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
+       int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
 
        if (off >= 0) {
                off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
                if (off > 0)
                        printf("WARNING enable to set clock-frequency "
-                               "for %s: %s\n", alias, fdt_strerror(off));
+                               "for %s: %s\n", compat, fdt_strerror(off));
        }
 }
 
@@ -317,14 +342,17 @@ static void ft_fixup_dpaa_clks(void *blob)
        sys_info_t sysinfo;
 
        get_sys_info(&sysinfo);
-       ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]);
+       ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+                       sysinfo.freqFMan[0]);
 
 #if (CONFIG_SYS_NUM_FMAN == 2)
-       ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]);
+       ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+                       sysinfo.freqFMan[1]);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_PME
-       ft_fixup_clks(blob, "pme", sysinfo.freqPME);
+       do_fixup_by_compat_u32(blob, "fsl,pme",
+               "clock-frequency", sysinfo.freqPME, 1);
 #endif
 }
 #else
@@ -400,12 +428,17 @@ void ft_cpu_setup(void *blob, bd_t *bd)
                "clock-frequency", bd->bi_brgfreq, 1);
 #endif
 
+#ifdef CONFIG_FSL_CORENET
+       do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
+               "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+#endif
+
        fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
 #ifdef CONFIG_MP
        ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
-#endif
        ft_fixup_num_cores(blob);
+#endif
 
        ft_fixup_cache(blob);
 
@@ -414,4 +447,18 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
 
        ft_fixup_dpaa_clks(blob);
+
+#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
+       fdt_portal(blob, "fsl,bman-portal", "bman-portals",
+                       (u64)CONFIG_SYS_BMAN_MEM_PHYS,
+                       CONFIG_SYS_BMAN_MEM_SIZE);
+#endif
+
+#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
+       fdt_portal(blob, "fsl,qman-portal", "qman-portals",
+                       (u64)CONFIG_SYS_QMAN_MEM_PHYS,
+                       CONFIG_SYS_QMAN_MEM_SIZE);
+
+       fdt_fixup_qportals(blob);
+#endif
 }