#include <fsl_esdhc.h>
#include <asm/cache.h>
#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif /* CONFIG_FSL_CORENET */
#ifdef CONFIG_DDR_CLK_FREQ
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- volatile u32 *brp,*orp;
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile u8* dummy = NULL;
int upmmask;
}
/* Find the address for the dummy write transaction */
- for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
- i++, brp += 2, orp += 2) {
-
- /* Look for a valid BR with selected UPM */
- if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
- dummy = (volatile u8*)(in_be32(brp) & BR_BA);
+ for (i = 0; i < 8; i++) {
+ if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+ dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
break;
}
}
return 0;
#endif
}
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs, BR0/OR0, and TLBs
+ */
+void mpc85xx_reginfo(void)
+{
+ print_tlbcam();
+ print_laws();
+ print_lbc_regs();
+}