mpc85xx: Add reginfo command

[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 0cc6e0323f2e8331a4ff9ef5daa7b5023ad907f3..790a6a4a4501c5b5453343663b889baaa651f4fe 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -32,6 +32,8 @@
 #include <fsl_esdhc.h>
 #include <asm/cache.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,21 +46,19 @@ int checkcpu (void)
        uint major, minor;
        struct cpu_type *cpu;
        char buf1[32], buf2[32];
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_CORENET
-       u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
-               >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
-#else
+#endif /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
        u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
                >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#endif
 #else
 #ifdef CONFIG_FSL_CORENET
-       u32 ddr_sync = 0;
+       u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+               >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
 #else
        u32 ddr_ratio = 0;
-#endif
+#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
        int i;
 
@@ -188,7 +188,7 @@ int checkcpu (void)
 
 /* ------------------------------------------------------------------------- */
 
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
@@ -259,8 +259,7 @@ void upmconfig (uint upm, uint * table, uint size)
 {
        int i, mdr, mad, old_mad = 0;
        volatile u32 *mxmr;
-       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-       volatile u32 *brp,*orp;
+       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
        volatile u8* dummy = NULL;
        int upmmask;
 
@@ -283,12 +282,9 @@ void upmconfig (uint upm, uint * table, uint size)
        }
 
        /* Find the address for the dummy write transaction */
-       for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
-                i++, brp += 2, orp += 2) {
-
-               /* Look for a valid BR with selected UPM */
-               if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
-                       dummy = (volatile u8*)(in_be32(brp) & BR_BA);
+       for (i = 0; i < 8; i++) {
+               if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+                       dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
                        break;
                }
        }
@@ -328,3 +324,14 @@ int cpu_mmc_init(bd_t *bis)
        return 0;
 #endif
 }
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs, BR0/OR0, and TLBs
+ */
+void mpc85xx_reginfo(void)
+{
+       print_tlbcam();
+       print_laws();
+       print_lbc_regs();
+}