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Merge branch 'u-boot/master' into 'u-boot-arm/master'
[oweals/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 66bc6a2ea362725f25a9bdedc131a7a98fec1dc8..3e99b079c74a5f613409fd70491d7882ae9e17c4 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -17,12 +17,12 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_lbc.h>
 #include <post.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -135,81 +135,82 @@ int checkcpu (void)
                if (!(i & 3))
                        printf ("\n       ");
                printf("CPU%d:%-4s MHz, ", core,
-                       strmhz(buf1, sysinfo.freqProcessor[core]));
+                       strmhz(buf1, sysinfo.freq_processor[core]));
        }
-       printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+       printf("\n       CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
+       printf("\n");
 
 #ifdef CONFIG_FSL_CORENET
        if (ddr_sync == 1) {
                printf("       DDR:%-4s MHz (%s MT/s data rate) "
                        "(Synchronous), ",
-                       strmhz(buf1, sysinfo.freqDDRBus/2),
-                       strmhz(buf2, sysinfo.freqDDRBus));
+                       strmhz(buf1, sysinfo.freq_ddrbus/2),
+                       strmhz(buf2, sysinfo.freq_ddrbus));
        } else {
                printf("       DDR:%-4s MHz (%s MT/s data rate) "
                        "(Asynchronous), ",
-                       strmhz(buf1, sysinfo.freqDDRBus/2),
-                       strmhz(buf2, sysinfo.freqDDRBus));
+                       strmhz(buf1, sysinfo.freq_ddrbus/2),
+                       strmhz(buf2, sysinfo.freq_ddrbus));
        }
 #else
        switch (ddr_ratio) {
        case 0x0:
                printf("       DDR:%-4s MHz (%s MT/s data rate), ",
-                       strmhz(buf1, sysinfo.freqDDRBus/2),
-                       strmhz(buf2, sysinfo.freqDDRBus));
+                       strmhz(buf1, sysinfo.freq_ddrbus/2),
+                       strmhz(buf2, sysinfo.freq_ddrbus));
                break;
        case 0x7:
                printf("       DDR:%-4s MHz (%s MT/s data rate) "
                        "(Synchronous), ",
-                       strmhz(buf1, sysinfo.freqDDRBus/2),
-                       strmhz(buf2, sysinfo.freqDDRBus));
+                       strmhz(buf1, sysinfo.freq_ddrbus/2),
+                       strmhz(buf2, sysinfo.freq_ddrbus));
                break;
        default:
                printf("       DDR:%-4s MHz (%s MT/s data rate) "
                        "(Asynchronous), ",
-                       strmhz(buf1, sysinfo.freqDDRBus/2),
-                       strmhz(buf2, sysinfo.freqDDRBus));
+                       strmhz(buf1, sysinfo.freq_ddrbus/2),
+                       strmhz(buf2, sysinfo.freq_ddrbus));
                break;
        }
 #endif
 
 #if defined(CONFIG_FSL_LBC)
-       if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
-               printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+       if (sysinfo.freq_localbus > LCRR_CLKDIV) {
+               printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
        } else {
                printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
-                      sysinfo.freqLocalBus);
+                      sysinfo.freq_localbus);
        }
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-       printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+       printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
 #endif
 
 #ifdef CONFIG_CPM2
-       printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
+       printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
 #endif
 
 #ifdef CONFIG_QE
-       printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
+       printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
        for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
                printf("       FMAN%d: %s MHz\n", i + 1,
-                       strmhz(buf1, sysinfo.freqFMan[i]));
+                       strmhz(buf1, sysinfo.freq_fman[i]));
        }
 #endif
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-       printf("       QMAN:  %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
+       printf("       QMAN:  %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
 #endif
 
 #ifdef CONFIG_SYS_DPAA_PME
-       printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
+       printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
 #endif
 
-       puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
+       puts("L1:    D-cache 32 KiB enabled\n       I-cache 32 KiB enabled\n");
 
 #ifdef CONFIG_FSL_CORENET
        /* Display the RCW, so that no one gets confused as to what RCW
@@ -415,7 +416,7 @@ static void dump_spd_ddr_reg(void)
        int i, j, k, m;
        u8 *p_8;
        u32 *p_32;
-       ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+       struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
        generic_spd_eeprom_t
                spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
 
@@ -452,21 +453,21 @@ static void dump_spd_ddr_reg(void)
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
                switch (i) {
                case 0:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
                        break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
                case 1:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
                case 2:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
                case 3:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
                        break;
 #endif
                default:
@@ -481,7 +482,7 @@ static void dump_spd_ddr_reg(void)
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
                printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
        puts("\n");
-       for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+       for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
                m = 0;
                printf("%6d (0x%04x)", k * 4, k * 4);
                for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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