tsec1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC1CM value */
+ /* unknown SCCR_TSEC1CM value */
return -2;
}
#endif
usbdr_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBDRCM value */
+ /* unknown SCCR_USBDRCM value */
return -3;
}
#endif
tsec2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC2CM value */
+ /* unknown SCCR_TSEC2CM value */
return -4;
}
#elif defined(CONFIG_MPC8313)
usbmph_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBMPHCM value */
+ /* unknown SCCR_USBMPHCM value */
return -5;
}
enc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_ENCCM value */
+ /* unknown SCCR_ENCCM value */
return -7;
}
#endif
sdhc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SDHCCM value */
+ /* unknown SCCR_SDHCCM value */
return -8;
}
#endif
tdm_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TDMCM value */
+ /* unknown SCCR_TDMCM value */
return -8;
}
#endif
pciexp1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP1CM value */
+ /* unknown SCCR_PCIEXP1CM value */
return -9;
}
pciexp2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP2CM value */
+ /* unknown SCCR_PCIEXP2CM value */
return -10;
}
#endif
sata_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SATACM value */
+ /* unknown SCCR_SATA1CM value */
return -11;
}
#endif
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
- if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
- /* corecnf_tab_index is too high, possibly worng value */
+ if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
+ /* corecnf_tab_index is too high, possibly wrong value */
return -11;
}
switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
core_clk = 3 * csb_clk;
break;
default:
- /* unkown core to csb ratio */
+ /* unknown core to csb ratio */
return -13;
}