Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

[oweals/u-boot.git] / arch / powerpc / cpu / mpc83xx / spd_sdram.c

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 44aaa9abc2130b9b046f06698e93493f6e4fb9bd..f62e1b79d36a25957c8298b85baaa098b14212ed 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -8,23 +8,7 @@
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -46,10 +30,19 @@ void board_add_ram_info(int use_default)
        printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
                           >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
 
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+       if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
+               puts(", 16-bit");
+       else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
+               puts(", 32-bit");
+       else
+               puts(", unknown width");
+#else
        if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
                puts(", 32-bit");
        else
                puts(", 64-bit");
+#endif
 
        if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
                puts(", ECC on");
@@ -68,6 +61,12 @@ void board_add_ram_info(int use_default)
 #ifndef        CONFIG_SYS_READ_SPD
 #define CONFIG_SYS_READ_SPD    i2c_read
 #endif
+#ifndef SPD_EEPROM_OFFSET
+#define SPD_EEPROM_OFFSET      0
+#endif
+#ifndef SPD_EEPROM_ADDR_LEN
+#define SPD_EEPROM_ADDR_LEN     1
+#endif
 
 /*
  * Convert picoseconds into clock cycles (rounding up if needed).
@@ -134,7 +133,7 @@ long int spd_sdram()
        unsigned int memsize;
        unsigned int law_size;
        unsigned char caslat, caslat_ctrl;
-       unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+       unsigned int trfc, trfc_clk, trfc_low;
        unsigned int trcd_clk, trtp_clk;
        unsigned char cke_min_clk;
        unsigned char add_lat, wr_lat;
@@ -160,7 +159,8 @@ long int spd_sdram()
        isync();
 
        /* Read SPD parameters with I2C */
-       CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+       CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
+               SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
 #ifdef SPD_DEBUG
        spd_debug(&spd);
 #endif
@@ -526,7 +526,6 @@ long int spd_sdram()
         * so preadjust it down 8 first before splitting it up.
         */
        trfc_low = (trfc_clk - 8) & 0xf;
-       trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
 
        ddr->timing_cfg_1 =
            (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |    /* PRETOACT */
@@ -562,6 +561,9 @@ long int spd_sdram()
         * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
         */
        wr_data_delay = 2;
+#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
+       wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
+#endif
 
        /*
         * Write Latency
@@ -601,6 +603,9 @@ long int spd_sdram()
         */
        cpo = 0;
        if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+#ifdef CONFIG_SYS_DDR_CPO
+               cpo = CONFIG_SYS_DDR_CPO;
+#else
                if (effective_data_rate == 266) {
                        cpo = 0x4;              /* READ_LAT + 1/2 */
                } else if (effective_data_rate == 333) {
@@ -611,6 +616,7 @@ long int spd_sdram()
                        /* Automatic calibration */
                        cpo = 0x1f;
                }
+#endif
        }
 
        ddr->timing_cfg_2 = (0
@@ -679,6 +685,9 @@ long int spd_sdram()
                ddr->sdram_mode =
                        (0
                         | (1 << (16 + 10))             /* DQS Differential disable */
+#ifdef CONFIG_SYS_DDR_MODE_WEAK
+                        | (1 << (16 + 1))              /* weak driver (~60%) */
+#endif
                         | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
                         | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
                         | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */