Merge git://git.denx.de/u-boot-i2c

[oweals/u-boot.git] / arch / powerpc / cpu / mpc83xx / pcie.c

diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 46a706d349da233891d241ae55526a0f117acb4e..28c25e5febba59176db4ebba14a5360b6156032d 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -5,20 +5,7 @@
  * Authors: Tony Li <tony.li@freescale.com>
  *          Anton Vorontsov <avorontsov@ru.mvista.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -48,11 +35,26 @@ static struct {
 
 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
 
+/* private structure for mpc83xx pcie hose */
+static struct mpc83xx_pcie_priv {
+       u8 index;
+} pcie_priv[PCIE_MAX_BUSES] = {
+       {
+               /* pcie controller 1 */
+               .index = 0,
+       },
+       {
+               /* pcie controller 2 */
+               .index = 1,
+       },
+};
+
 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
 {
        int bus = PCI_BUS(dev) - hose->first_busno;
        immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-       pex83xx_t *pex = &immr->pciexp[bus];
+       struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
+       pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
        struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
        u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
        u32 dev_base = bus << 24 | devfn << 16;
@@ -142,6 +144,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 
        hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
 
+       hose->priv_data = &pcie_priv[bus];
+
        pci_set_ops(hose,
                        pcie_read_config_byte,
                        pcie_read_config_word,
@@ -269,8 +273,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
        get_clocks();
        /* Configure the PCIE controller core clock ratio */
        out_le32(hose_cfg_base + PEX_GCLK_RATIO,
-               (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
-               / 333);
+               (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
+                       / 1000000) * 16) / 333);
        udelay(1000000);
 
        /* Do Type 1 bridge configuration */
@@ -295,6 +299,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 
        printf("PCIE%d: ", bus);
 
+#define PCI_LTSSM      0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0   0x16 /* L0 state */
        reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
        if (reg16 >= PCI_LTSSM_L0)
                printf("link\n");