#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
SCCR_PCICM |
#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
+ SCCR_PCIEXP1CM |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
+ SCCR_PCIEXP2CM |
+#endif
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
SCCR_TSECCM |
#endif
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
+ (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
+ (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
+#endif
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SICRL
__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
+#ifdef CONFIG_SYS_GPR1
+ __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
-#ifdef CONFIG_USB_EHCI_FSL
-#ifndef CONFIG_MPC834x
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
uint32_t temp;
- struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+ struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
/* Configure interface. */
setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
-#endif
}
int cpu_init_r (void)