mips: add initial support for qca956x referenced board

[oweals/u-boot.git] / arch / mips / mach-ath79 / include / mach / ar71xx_regs.h

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index 3506ed1da4911a5964d081f93ba9bc5085a0e039..5888f6eb288d303cb9fb1a3dc312141e76e1c58c 100644 (file)
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -194,6 +194,9 @@
 #define QCA956X_WMAC_BASE \
        (AR71XX_APB_BASE + 0x00100000)
 #define QCA956X_WMAC_SIZE                              0x20000
+#define QCA956X_RTC_BASE \
+       (AR71XX_APB_BASE + 0x00107000)
+#define QCA956X_RTC_SIZE                                       0x1000
 #define QCA956X_EHCI0_BASE                             0x1b000000
 #define QCA956X_EHCI1_BASE                             0x1b400000
 #define QCA956X_EHCI_SIZE                              0x200
@@ -201,6 +204,10 @@
        (AR71XX_APB_BASE + 0x00070000)
 #define QCA956X_GMAC_SIZE                              0x64
 
+#define QCA956X_SRIF_BASE \
+       (AR71XX_APB_BASE + 0x00116000)
+#define QCA956X_SRIF_SIZE                              0x1000
+
 /*
  * DDR_CTRL block
  */
@@ -278,6 +285,18 @@
 #define QCA953X_DDR_REG_CTL_CONF                       0x108
 #define QCA953X_DDR_REG_CONFIG3                                0x15c
 
+#define QCA956X_DDR_REG_TAP_CTRL2                      0x24
+#define QCA956X_DDR_REG_TAP_CTRL3                      0x28
+#define QCA956X_DDR_REG_DDR2_CONFIG                    0xb8
+#define QCA956X_DDR_REG_DDR2_EMR2                      0xbc
+#define QCA956X_DDR_REG_DDR2_EMR3                      0xc0
+#define QCA956X_DDR_REG_BURST                          0xc4
+#define QCA956X_DDR_REG_BURST2                         0xc8
+#define QCA956X_DDR_REG_TIMEOUT_MAX                    0xcc
+#define QCA956X_DDR_REG_FSM_WAIT_CTRL                  0xe4
+#define QCA956X_DDR_REG_CTL_CONF                       0x108
+#define QCA956X_DDR_REG_DDR3_CONFIG                    0x15c
+
 /*
  * PLL block
  */
@@ -519,6 +538,13 @@
 #define QCA956X_PLL_DDR_CONFIG_REG                     0x08
 #define QCA956X_PLL_DDR_CONFIG1_REG                    0x0c
 #define QCA956X_PLL_CLK_CTRL_REG                       0x10
+#define QCA956X_PLL_SWITCH_CLK_CTRL_REG                        0x28
+#define QCA956X_PLL_ETH_XMII_CTRL_REG                  0x30
+#define QCA956X_PLL_DDR_DIT_FRAC_REG                   0x38
+#define QCA956X_PLL_DDR_DIT2_FRAC_REG                  0x3c
+#define QCA956X_PLL_CPU_DIT_FRAC_REG                   0x40
+#define QCA956X_PLL_CPU_DIT2_FRAC_REG                  0x44
+#define QCA956X_PLL_ETH_SGMII_SERDES_REG               0x4c
 
 #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT            12
 #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK             0x1f
@@ -756,6 +782,17 @@
 #define QCA955X_RESET_MBOX                             BIT(1)
 #define QCA955X_RESET_I2S                              BIT(0)
 
+#define QCA956X_RESET_EXTERNAL                         BIT(28)
+#define QCA956X_RESET_FULL_CHIP                                BIT(24)
+#define QCA956X_RESET_GE1_MDIO                         BIT(23) /* Reserved in datasheet */
+#define QCA956X_RESET_GE0_MDIO                         BIT(22)
+#define QCA956X_RESET_GE1_MAC                          BIT(13) /* Reserved in datasheet */
+#define QCA956X_RESET_SGMII_ASSERT                     BIT(12)
+#define QCA956X_RESET_GE0_MAC                          BIT(9)
+#define QCA956X_RESET_SGMII                            BIT(8)
+#define QCA956X_RESET_SGMII_ANALOG                             BIT(2)
+#define QCA956X_RESET_SWITCH                           BIT(0)
+
 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN                  BIT(18)
 #define AR933X_BOOTSTRAP_DDR2                          BIT(13)
 #define AR933X_BOOTSTRAP_EEPBUSY                       BIT(4)
@@ -1099,8 +1136,12 @@
 #define QCA953X_GPIO_IN_MUX_UART0_SIN                  9
 #define QCA953X_GPIO_IN_MUX_SPI_DATA_IN                        8
 
+#define QCA956X_GPIO(x)                                        BIT(x)
+#define QCA956X_GPIO_MUX_MASK(x)                       (0xff << (x))
 #define QCA956X_GPIO_OUT_MUX_GE0_MDO                   32
 #define QCA956X_GPIO_OUT_MUX_GE0_MDC                   33
+#define QCA956X_GPIO_IN_MUX_UART0_SIN                  0x12
+#define QCA956X_GPIO_OUT_MUX_UART0_SOUT                        0x16
 
 #define AR71XX_GPIO_COUNT                              16
 #define AR7240_GPIO_COUNT                              18
@@ -1179,6 +1220,25 @@
 #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT                        13
 #define QCA953X_SRIF_DPLL2_OUTDIV_MASK                 0x7
 
+#define QCA956X_SRIF_BB_DPLL1_REG                      0x180
+#define QCA956X_SRIF_BB_DPLL2_REG                      0x184
+#define QCA956X_SRIF_BB_DPLL3_REG                      0x188
+
+#define QCA956X_SRIF_CPU_DPLL1_REG                     0xf00
+#define QCA956X_SRIF_CPU_DPLL2_REG                     0xf04
+#define QCA956X_SRIF_CPU_DPLL3_REG                     0xf08
+
+#define QCA956X_SRIF_DDR_DPLL1_REG                     0xec0
+#define QCA956X_SRIF_DDR_DPLL2_REG                     0xec4
+#define QCA956X_SRIF_DDR_DPLL3_REG                     0xec8
+
+#define QCA956X_SRIF_PCIE_DPLL1_REG                    0xc80
+#define QCA956X_SRIF_PCIE_DPLL2_REG                    0xc84
+#define QCA956X_SRIF_PCIE_DPLL3_REG                    0xc88
+
+#define QCA956X_SRIF_PMU1_REG                          0xcc0
+#define QCA956X_SRIF_PMU2_REG                          0xcc4
+
 /*
  * MII_CTRL block
  */
@@ -1261,4 +1321,17 @@
 #define QCA955X_ETH_CFG_RGMII_EN                       BIT(0)
 #define QCA955X_ETH_CFG_GE0_SGMII                      BIT(6)
 
+/*
+ * QCA956X GMAC Interface
+ */
+
+#define QCA956X_GMAC_REG_ETH_CFG                       0x00
+#define QCA956X_GMAC_REG_SGMII_RESET                   0x14
+#define QCA956X_GMAC_REG_SGMII_SERDES                  0x18
+#define QCA956X_GMAC_REG_MR_AN_CTRL                    0x1c
+#define QCA956X_GMAC_REG_SGMII_CONFIG                  0x34
+#define QCA956X_GMAC_REG_SGMII_DEBUG                   0x58
+
+#define QCA956X_ETH_CFG_GE0_SGMII                      BIT(6)
+
 #endif /* __ASM_AR71XX_H */