arm: juno: enable USB

[oweals/u-boot.git] / arch / mips / mach-ath79 / ar933x / ddr.c

diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 7f20d348855597f0fac635faffc79efe256bcd2e..2cf0b2cb1f9f8a433fdc7ae1e7925488872687b4 100644 (file)
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  * Based on Atheros LSDK/QSDK
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include <common.h>
@@ -10,9 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <mach/ath79.h>
 
 #define DDR_CTRL_UPD_EMR3S      BIT(5)
 #define DDR_CTRL_UPD_EMR2S      BIT(4)
@@ -114,7 +111,7 @@ void ddr_init(void)
        writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
        writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 
-       val = get_bootstrap();
+       val = ath79_get_bootstrap();
        if (val & AR933X_BOOTSTRAP_DDR2) {
                /* AHB maximum timeout */
                writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);