Merge branch '2020-05-18-reduce-size-of-common.h'

[oweals/u-boot.git] / arch / mips / mach-ath79 / ar933x / ddr.c

diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 74e8e80ea72546f23ab5abaf9c79581842d392ef..09166ecf8f0757e78bfdf535bf79f869a5205dd6 100644 (file)
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -1,18 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  * Based on Atheros LSDK/QSDK
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
 #include <asm/types.h>
+#include <linux/bitops.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <mach/ath79.h>
 
 #define DDR_CTRL_UPD_EMR3S      BIT(5)
 #define DDR_CTRL_UPD_EMR2S      BIT(4)
@@ -21,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_CTRL_UPD_EMRS       BIT(1)
 #define DDR_CTRL_UPD_MRS        BIT(0)
 
-#define DDR_REFRESH_EN          (1 << 14)
+#define DDR_REFRESH_EN          BIT(14)
 #define DDR_REFRESH_M           0x3ff
 #define DDR_REFRESH(x)          ((x) & 0x3ff)
 #define DDR_REFRESH_VAL_25M     (DDR_REFRESH_EN | DDR_REFRESH(390))
@@ -48,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_CAS_L_M             0x17
 #define DDR_CAS_L_S             27
 #define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
-#define DDR_OPEN                (1 << 30)
+#define DDR_OPEN                BIT(30)
 #define DDR_CONF_REG_VAL        (DDR_TRAS(16) | DDR_TRCD(6) | \
                                 DDR_TRP(6) | DDR_TRRD(4) | \
                                 DDR_TRFC(30) | DDR_TMRD(15) | \
@@ -57,10 +55,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_BURST_LEN_S         0
 #define DDR_BURST_LEN_M         0xf
 #define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
-#define DDR_BURST_TYPE          (1 << 4)
-#define DDR_CNTL_OE_EN          (1 << 5)
-#define DDR_PHASE_SEL           (1 << 6)
-#define DDR_CKE                 (1 << 7)
+#define DDR_BURST_TYPE          BIT(4)
+#define DDR_CNTL_OE_EN          BIT(5)
+#define DDR_PHASE_SEL           BIT(6)
+#define DDR_CKE                 BIT(7)
 #define DDR_TWR_S               8
 #define DDR_TWR_M               0xf
 #define DDR_TWR(x)              ((x) << DDR_TWR_S)
@@ -76,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_G_OPEN_L_S          26
 #define DDR_G_OPEN_L_M          0xf
 #define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
-#define DDR_HALF_WIDTH_LOW      (1 << 31)
+#define DDR_HALF_WIDTH_LOW      BIT(31)
 #define DDR_CONF2_REG_VAL       (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
                                 DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
                                 DDR_TRTP(8) | DDR_TWTR(14) | \
@@ -114,7 +112,7 @@ void ddr_init(void)
        writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
        writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 
-       val = get_bootstrap();
+       val = ath79_get_bootstrap();
        if (val & AR933X_BOOTSTRAP_DDR2) {
                /* AHB maximum timeout */
                writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
@@ -268,6 +266,8 @@ void ddr_tap_tuning(void)
        dir = 1;
        tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
        val = tap;
+       upper = tap;
+       lower = tap;
        while (!done) {
                err = 0;