Merge branch 'master' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / arch / mips / lib / cache_init.S

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index cbd04bd2f3bab5891134385b8751220d2e45649e..137d7283ffefb1f81a60b81fbfb5c559f798787e 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -113,6 +113,8 @@ LEAF(mips_cache_reset)
        l1_info t3, t9, MIPS_CONF1_DA_SHIFT
 #endif
 
+#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+
        /* Determine the largest L1 cache size */
 #if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
@@ -134,41 +136,51 @@ LEAF(mips_cache_reset)
        f_fill64        a0, -64, zero
        bne             a0, a1, 2b
 
+#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
+
        /*
-        * The caches are probably in an indeterminate state,
-        * so we force good parity into them by doing an
-        * invalidate, load/fill, invalidate for each line.
+        * The TagLo registers used depend upon the CPU implementation, but the
+        * architecture requires that it is safe for software to write to both
+        * TagLo selects 0 & 2 covering supported cases.
         */
+       mtc0            zero, CP0_TAGLO
+       mtc0            zero, CP0_TAGLO, 2
 
        /*
-        * Assume bottom of RAM will generate good parity for the cache.
+        * The caches are probably in an indeterminate state, so we force good
+        * parity into them by doing an invalidate for each line. If
+        * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
+        * perform a load/fill & a further invalidate for each line, assuming
+        * that the bottom of RAM (having just been cleared) will generate good
+        * parity for the cache.
         */
 
        /*
         * Initialize the I-cache first,
         */
        blez            t2, 1f
-       mtc0            zero, CP0_TAGLO
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, t2
        /* clear tag to invalidate */
        cache_loop      t0, t1, t8, INDEX_STORE_TAG_I
+#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
        /* fill once, so data field parity is correct */
        PTR_LI          t0, INDEX_BASE
        cache_loop      t0, t1, t8, FILL
        /* invalidate again - prudent but not strictly neccessary */
        PTR_LI          t0, INDEX_BASE
        cache_loop      t0, t1, t8, INDEX_STORE_TAG_I
+#endif
 
        /*
         * then initialize D-cache.
         */
 1:     blez            t3, 3f
-       mtc0            zero, CP0_TAGLO
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, t3
        /* clear all tags */
        cache_loop      t0, t1, t9, INDEX_STORE_TAG_D
+#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
        /* load from each line (in cached space) */
        PTR_LI          t0, INDEX_BASE
 2:     LONG_L          zero, 0(t0)
@@ -177,6 +189,7 @@ LEAF(mips_cache_reset)
        /* clear all tags */
        PTR_LI          t0, INDEX_BASE
        cache_loop      t0, t1, t9, INDEX_STORE_TAG_D
+#endif
 
 3:     jr      ra
        END(mips_cache_reset)