*/
#include <common.h>
+#include <cpu_func.h>
#include <asm/cacheops.h>
#ifdef CONFIG_MIPS_L2_CACHE
#include <asm/cm.h>
#ifdef CONFIG_MIPS_L2_CACHE
return gd->arch.l2_line_size;
#else
- return 0;
+ return CONFIG_SYS_SCACHE_LINE_SIZE;
#endif
}
instruction_hazard_barrier();
}
-void flush_dcache_range(ulong start_addr, ulong stop)
+void __weak flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
unsigned long slsize = scache_line_size();