#define CP0_ENTRYLO0 $2
#define CP0_ENTRYLO1 $3
#define CP0_CONF $3
+#define CP0_GLOBALNUMBER $3, 1
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
#define STATUSF_IP14 (_ULCAST_(1) << 6)
#define STATUSB_IP15 7
#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define ST0_IMPL (_ULCAST_(3) << 16)
#define ST0_CH 0x00040000
#define ST0_NMI 0x00080000
#define ST0_SR 0x00100000
#define CAUSEB_BD 31
#define CAUSEF_BD (_ULCAST_(1) << 31)
+/*
+ * Bits in the coprocessor 0 EBase register.
+ */
+#define EBASE_CPUNUM 0x3ff
+
/*
* Bits in the coprocessor 0 config register.
*/
#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
+#define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
/*
#define MIPS_CONF1_TLBS_SIZE (6)
#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
+#define MIPS_CONF2_SA_SHF 0
#define MIPS_CONF2_SA (_ULCAST_(15) << 0)
+#define MIPS_CONF2_SL_SHF 4
#define MIPS_CONF2_SL (_ULCAST_(15) << 4)
+#define MIPS_CONF2_SS_SHF 8
#define MIPS_CONF2_SS (_ULCAST_(15) << 8)
+#define MIPS_CONF2_L2B (_ULCAST_(1) << 12)
#define MIPS_CONF2_SU (_ULCAST_(15) << 12)
#define MIPS_CONF2_TA (_ULCAST_(15) << 16)
#define MIPS_CONF2_TL (_ULCAST_(15) << 20)
#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
+#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
+#define MIPS_CONF5_L2C (_ULCAST_(1) << 10)
#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
#define MIPS_CONF5_CV (_ULCAST_(1) << 29)