SPDX: Convert all of our single license tags to Linux Kernel style

[oweals/u-boot.git] / arch / mips / include / asm / cache.h

diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 0dfb54ef4dda75e49be553569ce10f0af61e4894..00696e672de0222037266bcd81f316a226404683 100644 (file)
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -1,21 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __MIPS_CACHE_H__
 #define __MIPS_CACHE_H__
 
+#define L1_CACHE_SHIFT         CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN      (L1_CACHE_BYTES)
+
 /*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
+#ifndef __ASSEMBLY__
+/**
+ * mips_cache_probe() - Probe the properties of the caches
+ *
+ * Call this to probe the properties such as line sizes of the caches
+ * present in the system, if any. This must be done before cache maintenance
+ * functions such as flush_cache may be called.
  */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN      128
+void mips_cache_probe(void);
 #endif
 
 #endif /* __MIPS_CACHE_H__ */