bmips: enable vr-3032u nand support

[oweals/u-boot.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b1b1d7d00319145ad1a76392ab05d36f96ccbf7..f5d81b822c48d5500cf805a3ae7e8c311737f379 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -59,6 +59,11 @@ config ARCH_ATH79
        select OF_CONTROL
        imply CMD_DM
 
+config ARCH_MSCC
+       bool "Support MSCC VCore-III"
+       select OF_CONTROL
+       select DM
+
 config ARCH_BMIPS
        bool "Support BMIPS SoCs"
        select CLK
@@ -69,8 +74,8 @@ config ARCH_BMIPS
        select SYSRESET
        imply CMD_DM
 
-config ARCH_MT7620
-       bool "Support MT7620/7688 SoCs"
+config ARCH_MTMIPS
+       bool "Support MediaTek MIPS platforms"
        imply CMD_DM
        select DISPLAY_CPUINFO
        select DM
@@ -79,7 +84,7 @@ config ARCH_MT7620
        select DM_SERIAL
        imply DM_SPI
        imply DM_SPI_FLASH
-       select ARCH_MISC_INIT if WATCHDOG
+       select LAST_STAGE_INIT
        select MIPS_TUNE_24KC
        select OF_CONTROL
        select ROM_EXCEPTION_VECTORS
@@ -88,6 +93,12 @@ config ARCH_MT7620
        select SUPPORTS_LITTLE_ENDIAN
        select SYSRESET
 
+config ARCH_JZ47XX
+       bool "Support Ingenic JZ47xx"
+       select SUPPORT_SPL
+       select OF_CONTROL
+       select DM
+
 config MACH_PIC32
        bool "Support Microchip PIC32"
        select DM
@@ -138,9 +149,11 @@ source "board/imgtec/xilfpga/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-mscc/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
-source "arch/mips/mach-mt7620/Kconfig"
+source "arch/mips/mach-mtmips/Kconfig"
 
 if MIPS
 
@@ -395,9 +408,17 @@ config SYS_ICACHE_LINE_SIZE
        help
          The size of L1 Icache lines, if known at compile time.
 
+config SYS_SCACHE_LINE_SIZE
+       int
+       default 0
+       help
+         The size of L2 cache lines, if known at compile time.
+
+
 config SYS_CACHE_SIZE_AUTO
        def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
-               SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
+               SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
+               SYS_SCACHE_LINE_SIZE = 0
        help
          Select this (or let it be auto-selected by not defining any cache
          sizes) in order to allow U-Boot to automatically detect the sizes