microblaze: Flush caches before enabling them

[oweals/u-boot.git] / arch / microblaze / cpu / irq.S

diff --git a/arch/microblaze/cpu/irq.S b/arch/microblaze/cpu/irq.S
index 47bba36f21f61095a8ff6a9d0d7eef91f4e25b84..8c76a73e95de02346dde87922de0f56cbd829a64 100644 (file)
--- a/arch/microblaze/cpu/irq.S
+++ b/arch/microblaze/cpu/irq.S
@@ -60,7 +60,6 @@ _interrupt_handler:
        addik   r1, r1, -124
        brlid   r15, interrupt_handler
        nop
-       nop
        addik   r1, r1, 124
        lwi     r31, r1, -120
        lwi     r30, r1, -116
@@ -93,22 +92,6 @@ _interrupt_handler:
        lwi     r3, r1, -8
        lwi     r2, r1, -4
 
-       /* enable_interrupt */
-#ifdef XILINX_USE_MSR_INSTR
-       msrset  r0, 2
-#else
-       /* FIXME unstable in stressed mode - two irqs */
-       nop
-       addi    r1, r1, -4
-       swi     r12, r1, 0
-       mfs     r12, rmsr
-       ori     r12, r12, 2
-       mts     rmsr, r12
-       lwi     r12, r1, 0
-       addi    r1, r1, 4
-       nop
-#endif
-       bra     r14
-       nop
+       rtid    r14, 0
        nop
        .size _interrupt_handler,.-_interrupt_handler