usb: UniPhier: support OF configuration

[oweals/u-boot.git] / arch / arm / mvebu-common / dram.c

diff --git a/arch/arm/mvebu-common/dram.c b/arch/arm/mvebu-common/dram.c
index bb5989b3e85afcabad545c21e53d31a4e0e23e53..db18791a8627e77f9baba41199a9ba5fba3af37c 100644 (file)
--- a/arch/arm/mvebu-common/dram.c
+++ b/arch/arm/mvebu-common/dram.c
@@ -10,31 +10,31 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct kw_sdram_bank {
+struct sdram_bank {
        u32     win_bar;
        u32     win_sz;
 };
 
-struct kw_sdram_addr_dec {
-       struct kw_sdram_bank    sdram_bank[4];
+struct sdram_addr_dec {
+       struct sdram_bank sdram_bank[4];
 };
 
-#define KW_REG_CPUCS_WIN_ENABLE                (1 << 0)
-#define KW_REG_CPUCS_WIN_WR_PROTECT    (1 << 1)
-#define KW_REG_CPUCS_WIN_WIN0_CS(x)    (((x) & 0x3) << 2)
-#define KW_REG_CPUCS_WIN_SIZE(x)       (((x) & 0xff) << 24)
+#define REG_CPUCS_WIN_ENABLE           (1 << 0)
+#define REG_CPUCS_WIN_WR_PROTECT       (1 << 1)
+#define REG_CPUCS_WIN_WIN0_CS(x)       (((x) & 0x3) << 2)
+#define REG_CPUCS_WIN_SIZE(x)          (((x) & 0xff) << 24)
 
 /*
- * kw_sdram_bar - reads SDRAM Base Address Register
+ * mvebu_sdram_bar - reads SDRAM Base Address Register
  */
-u32 kw_sdram_bar(enum memory_bank bank)
+u32 mvebu_sdram_bar(enum memory_bank bank)
 {
-       struct kw_sdram_addr_dec *base =
-               (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+       struct sdram_addr_dec *base =
+               (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
        u32 result = 0;
        u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
 
@@ -46,31 +46,31 @@ u32 kw_sdram_bar(enum memory_bank bank)
 }
 
 /*
- * kw_sdram_bs_set - writes SDRAM Bank size
+ * mvebu_sdram_bs_set - writes SDRAM Bank size
  */
-static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
 {
-       struct kw_sdram_addr_dec *base =
-               (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+       struct sdram_addr_dec *base =
+               (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
        /* Read current register value */
        u32 reg = readl(&base->sdram_bank[bank].win_sz);
 
        /* Clear window size */
-       reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+       reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
 
        /* Set new window size */
-       reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+       reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
 
        writel(reg, &base->sdram_bank[bank].win_sz);
 }
 
 /*
- * kw_sdram_bs - reads SDRAM Bank size
+ * mvebu_sdram_bs - reads SDRAM Bank size
  */
-u32 kw_sdram_bs(enum memory_bank bank)
+u32 mvebu_sdram_bs(enum memory_bank bank)
 {
-       struct kw_sdram_addr_dec *base =
-               (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+       struct sdram_addr_dec *base =
+               (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
        u32 result = 0;
        u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
 
@@ -81,15 +81,16 @@ u32 kw_sdram_bs(enum memory_bank bank)
        return result;
 }
 
-void kw_sdram_size_adjust(enum memory_bank bank)
+void mvebu_sdram_size_adjust(enum memory_bank bank)
 {
        u32 size;
 
        /* probe currently equipped RAM size */
-       size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
+       size = get_ram_size((void *)mvebu_sdram_bar(bank),
+                           mvebu_sdram_bs(bank));
 
        /* adjust SDRAM window size accordingly */
-       kw_sdram_bs_set(bank, size);
+       mvebu_sdram_bs_set(bank, size);
 }
 
 #ifndef CONFIG_SYS_BOARD_DRAM_INIT
@@ -99,8 +100,8 @@ int dram_init(void)
 
        gd->ram_size = 0;
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-               gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-               gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+               gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
+               gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
                /*
                 * It is assumed that all memory banks are consecutive
                 * and without gaps.