ARM: uniphier: enable SSC for more PLLs for LD20 SoC

[oweals/u-boot.git] / arch / arm / mach-uniphier / sg-regs.h

diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 4044245ee1854dcd390542f777cd1636d8b03178..a179d615be9e0c77b59245cf762ac3848c186140 100644 (file)
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -50,14 +50,18 @@
 #define SG_MEMCONF_CH2_SZ_128M         ((0x0 << 26) | (0x02 << 16))
 #define SG_MEMCONF_CH2_SZ_256M         ((0x0 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_512M         ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_SZ_1G           ((0x1 << 26) | (0x01 << 16))
 #define SG_MEMCONF_CH2_NUM_MASK                (0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_1           (0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_2           (0x0 << 24)
-/* PH1-LD6b, ProXstream2 only */
+/* PH1-LD6b, ProXstream2, PH1-LD20 only */
 #define SG_MEMCONF_CH2_DISABLE         (0x1 << 21)
 
 #define SG_MEMCONF_SPARSEMEM           (0x1 << 4)
 
+#define SG_ETPHYPSHUT                  (SG_CTRL_BASE | 0x554)
+#define SG_ETPHYCNT                    (SG_CTRL_BASE | 0x550)
+
 /* Pin Control */
 #define SG_PINCTRL_BASE                        (SG_CTRL_BASE | 0x1000)