Merge branch '2019-05-28-master-imports'

[oweals/u-boot.git] / arch / arm / mach-uniphier / sc64-regs.h

diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index d0a51f239c3808c2beede8c86631089d3b5bed59..83f34e3faf1efb57c40e8c89e25e919aee785b02 100644 (file)
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * UniPhier SC (System Control) block registers for ARMv8 SoCs
  *
  * Copyright (C) 2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef SC64_REGS_H
@@ -15,34 +14,16 @@
 #define SC_RSTCTRL             (SC_BASE_ADDR | 0x2000)
 #define SC_RSTCTRL3            (SC_BASE_ADDR | 0x2008)
 #define SC_RSTCTRL4            (SC_BASE_ADDR | 0x200c)
-#define   SC_RSTCTRL4_ETHER            (1 << 6)
-#define   SC_RSTCTRL4_NAND             (1 << 0)
 #define SC_RSTCTRL5            (SC_BASE_ADDR | 0x2010)
 #define SC_RSTCTRL6            (SC_BASE_ADDR | 0x2014)
 #define SC_RSTCTRL7            (SC_BASE_ADDR | 0x2018)
-#define   SC_RSTCTRL7_UMCSB            (1 << 16)
-#define   SC_RSTCTRL7_UMCA2            (1 << 10)
-#define   SC_RSTCTRL7_UMCA1            (1 << 9)
-#define   SC_RSTCTRL7_UMCA0            (1 << 8)
-#define   SC_RSTCTRL7_UMC32            (1 << 2)
-#define   SC_RSTCTRL7_UMC31            (1 << 1)
-#define   SC_RSTCTRL7_UMC30            (1 << 0)
 
 #define SC_CLKCTRL             (SC_BASE_ADDR | 0x2100)
 #define SC_CLKCTRL3            (SC_BASE_ADDR | 0x2108)
 #define SC_CLKCTRL4            (SC_BASE_ADDR | 0x210c)
-#define   SC_CLKCTRL4_MIO              (1 << 10)
-#define   SC_CLKCTRL4_STDMAC           (1 << 8)
-#define   SC_CLKCTRL4_PERI             (1 << 7)
-#define   SC_CLKCTRL4_ETHER            (1 << 6)
-#define   SC_CLKCTRL4_NAND             (1 << 0)
 #define SC_CLKCTRL5            (SC_BASE_ADDR | 0x2110)
 #define SC_CLKCTRL6            (SC_BASE_ADDR | 0x2114)
 #define SC_CLKCTRL7            (SC_BASE_ADDR | 0x2118)
-#define   SC_CLKCTRL7_UMCSB            (1 << 16)
-#define   SC_CLKCTRL7_UMC32            (1 << 2)
-#define   SC_CLKCTRL7_UMC31            (1 << 1)
-#define   SC_CLKCTRL7_UMC30            (1 << 0)
 
 #define SC_CA72_GEARST         (SC_BASE_ADDR | 0x8000)
 #define SC_CA72_GEARSET                (SC_BASE_ADDR | 0x8004)