rockchip: dts: rk3399-firely: add 'same-as-spl'

[oweals/u-boot.git] / arch / arm / mach-uniphier / sc-regs.h

diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
index 474b82d24309143fe41c83cdcd4e782b9fb914dd..b105335f693108ad2a45dddf64217e9f9ab2bb68 100644 (file)
--- a/arch/arm/mach-uniphier/sc-regs.h
+++ b/arch/arm/mach-uniphier/sc-regs.h
@@ -1,19 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * UniPhier SC (System Control) block registers
  *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  */
 
 #ifndef ARCH_SC_REGS_H
 #define ARCH_SC_REGS_H
 
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
-#define SC_BASE_ADDR                   0xf1840000
-#else
 #define SC_BASE_ADDR                   0x61840000
-#endif
 
 #define SC_DPLLOSCCTRL                 (SC_BASE_ADDR | 0x1110)
 #define SC_DPLLOSCCTRL_DPLLST          (0x1 << 1)
@@ -45,7 +42,6 @@
 #define SC_RSTCTRL_NRST_USB3B0         (0x1 << 17)     /* USB3 #0 bus */
 #define SC_RSTCTRL_NRST_USB3C0         (0x1 << 16)     /* USB3 #0 core */
 #define SC_RSTCTRL_NRST_ETHER          (0x1 << 12)
-#define SC_RSTCTRL_NRST_STDMAC         (0x1 << 10)
 #define SC_RSTCTRL_NRST_GIO            (0x1 <<  6)
 /* Pro4 or older */
 #define SC_RSTCTRL_NRST_UMC1           (0x1 <<  5)
@@ -68,12 +64,14 @@
 #define SC_RSTCTRL4_NRST_UMC31         (0x1 <<  5)     /* UMC ch1 */
 #define SC_RSTCTRL4_NRST_UMC30         (0x1 <<  4)     /* UMC ch0 */
 
+#define SC_RSTCTRL5                    (SC_BASE_ADDR | 0x2010)
+
+#define SC_RSTCTRL6                    (SC_BASE_ADDR | 0x2014)
+
 #define SC_CLKCTRL                     (SC_BASE_ADDR | 0x2104)
 #define SC_CLKCTRL_CEN_USB31           (0x1 << 17)     /* USB3 #1 */
 #define SC_CLKCTRL_CEN_USB30           (0x1 << 16)     /* USB3 #0 */
 #define SC_CLKCTRL_CEN_ETHER           (0x1 << 12)
-#define SC_CLKCTRL_CEN_MIO             (0x1 << 11)
-#define SC_CLKCTRL_CEN_STDMAC          (0x1 << 10)
 #define SC_CLKCTRL_CEN_GIO             (0x1 <<  6)
 /* Pro4 or older */
 #define SC_CLKCTRL_CEN_UMC             (0x1 <<  4)