+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
-#include <libfdt.h>
+#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/printk.h>
#include "init.h"
#include "micro-support-card.h"
-#include "sg-regs.h"
#include "soc-info.h"
-DECLARE_GLOBAL_DATA_PTR;
-
-static void uniphier_setup_xirq(void)
+#ifdef CONFIG_ARCH_UNIPHIER_LD20
+static void uniphier_ld20_misc_init(void)
{
- const void *fdt = gd->fdt_blob;
- int soc_node, aidet_node;
- const u32 *val;
- unsigned long aidet_base;
- u32 tmp;
-
- soc_node = fdt_path_offset(fdt, "/soc");
- if (soc_node < 0)
- return;
-
- aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
- if (aidet_node < 0)
- return;
-
- val = fdt_getprop(fdt, aidet_node, "reg", NULL);
- if (!val)
- return;
-
- aidet_base = fdt32_to_cpu(*val);
-
- tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
- tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
- writel(tmp, aidet_base + 8);
-
- tmp = readl(0x55000090); /* IRQCTL */
- tmp |= 0x000000ff;
- writel(tmp, 0x55000090);
+ /* ES1 errata: increase VDD09 supply to suppress VBO noise */
+ if (uniphier_get_soc_revision() == 1) {
+ writel(0x00000003, 0x6184e004);
+ writel(0x00000100, 0x6184e040);
+ writel(0x0000b500, 0x6184e024);
+ writel(0x00000001, 0x6184e000);
+ }
}
-
-static void uniphier_nand_pin_init(bool cs2)
-{
-#ifdef CONFIG_NAND_DENALI
- if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
- pr_err("failed to init NAND pins\n");
#endif
-}
-
-int board_init(void)
-{
- const struct uniphier_board_data *bd;
- led_puts("U0");
+struct uniphier_initdata {
+ unsigned int soc_id;
+ void (*sbc_init)(void);
+ void (*pll_init)(void);
+ void (*clk_init)(void);
+ void (*misc_init)(void);
+};
- bd = uniphier_get_board_param();
- if (!bd)
- return -ENODEV;
-
- switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- case SOC_UNIPHIER_SLD3:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_sld3_pll_init();
- uniphier_ld4_clk_init();
- break;
-#endif
+static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
- case SOC_UNIPHIER_LD4:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_ld4_pll_init();
- uniphier_ld4_clk_init();
- break;
+ {
+ .soc_id = UNIPHIER_LD4_ID,
+ .sbc_init = uniphier_ld4_sbc_init,
+ .pll_init = uniphier_ld4_pll_init,
+ .clk_init = uniphier_ld4_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
- case SOC_UNIPHIER_PRO4:
- uniphier_nand_pin_init(false);
- led_puts("U1");
- uniphier_pro4_pll_init();
- uniphier_pro4_clk_init();
- break;
+ {
+ .soc_id = UNIPHIER_PRO4_ID,
+ .sbc_init = uniphier_sbc_init_savepin,
+ .pll_init = uniphier_pro4_pll_init,
+ .clk_init = uniphier_pro4_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
- case SOC_UNIPHIER_SLD8:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_ld4_pll_init();
- uniphier_ld4_clk_init();
- break;
+ {
+ .soc_id = UNIPHIER_SLD8_ID,
+ .sbc_init = uniphier_ld4_sbc_init,
+ .pll_init = uniphier_ld4_pll_init,
+ .clk_init = uniphier_ld4_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- case SOC_UNIPHIER_PRO5:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_pro5_clk_init();
- break;
+ {
+ .soc_id = UNIPHIER_PRO5_ID,
+ .sbc_init = uniphier_sbc_init_savepin,
+ .clk_init = uniphier_pro5_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
- case SOC_UNIPHIER_PXS2:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_pxs2_clk_init();
- break;
+ {
+ .soc_id = UNIPHIER_PXS2_ID,
+ .sbc_init = uniphier_pxs2_sbc_init,
+ .clk_init = uniphier_pxs2_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
- case SOC_UNIPHIER_LD6B:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_pxs2_clk_init();
- break;
+ {
+ .soc_id = UNIPHIER_LD6B_ID,
+ .sbc_init = uniphier_pxs2_sbc_init,
+ .clk_init = uniphier_pxs2_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- case SOC_UNIPHIER_LD11:
- uniphier_nand_pin_init(false);
- sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
- sg_set_iectrl(149);
- sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
- sg_set_iectrl(153);
- led_puts("U1");
- uniphier_ld11_clk_init();
- break;
+ {
+ .soc_id = UNIPHIER_LD11_ID,
+ .sbc_init = uniphier_ld11_sbc_init,
+ .pll_init = uniphier_ld11_pll_init,
+ .clk_init = uniphier_ld11_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- case SOC_UNIPHIER_LD20:
- uniphier_nand_pin_init(false);
- sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
- sg_set_iectrl(149);
- sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
- sg_set_iectrl(153);
- led_puts("U1");
- uniphier_ld20_pll_init(bd);
- uniphier_ld20_clk_init();
- cci500_init(2);
- break;
+ {
+ .soc_id = UNIPHIER_LD20_ID,
+ .sbc_init = uniphier_ld11_sbc_init,
+ .pll_init = uniphier_ld20_pll_init,
+ .clk_init = uniphier_ld20_clk_init,
+ .misc_init = uniphier_ld20_misc_init,
+ },
#endif
- default:
- break;
+#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
+ {
+ .soc_id = UNIPHIER_PXS3_ID,
+ .sbc_init = uniphier_pxs2_sbc_init,
+ .pll_init = uniphier_pxs3_pll_init,
+ .clk_init = uniphier_pxs3_clk_init,
+ },
+#endif
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata)
+
+int board_init(void)
+{
+ const struct uniphier_initdata *initdata;
+
+ led_puts("U0");
+
+ initdata = uniphier_get_initdata();
+ if (!initdata) {
+ pr_err("unsupported SoC\n");
+ return -EINVAL;
}
- uniphier_setup_xirq();
+ initdata->sbc_init();
+
+ support_card_init();
+
+ led_puts("U0");
+
+ if (initdata->pll_init)
+ initdata->pll_init();
+
+ led_puts("U1");
+
+ if (initdata->clk_init)
+ initdata->clk_init();
led_puts("U2");
- support_card_late_init();
+ if (initdata->misc_init)
+ initdata->misc_init();
led_puts("U3");
-#ifdef CONFIG_ARM64
- uniphier_smp_kick_all_cpus();
-#endif
+ support_card_late_init();
led_puts("Uboo");
projects / oweals / u-boot.git / blobdiff