+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <cpu_func.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/printk.h>
#include <linux/psci.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include <asm/psci.h>
#include <asm/secure.h>
+#include <asm/system.h>
#include "../debug.h"
#include "../soc-info.h"
static int uniphier_get_nr_cpus(void)
{
- switch (uniphier_get_soc_type()) {
- case SOC_UNIPHIER_SLD3:
- case SOC_UNIPHIER_PRO4:
- case SOC_UNIPHIER_PRO5:
+ switch (uniphier_get_soc_id()) {
+ case UNIPHIER_PRO4_ID:
+ case UNIPHIER_PRO5_ID:
return 2;
- case SOC_UNIPHIER_PXS2:
- case SOC_UNIPHIER_LD6B:
+ case UNIPHIER_PXS2_ID:
+ case UNIPHIER_LD6B_ID:
return 4;
default:
return 1;
}
if (!timeout)
- printf("warning: some of secondary CPUs may not boot\n");
+ pr_warn("warning: some of secondary CPUs may not boot\n");
uniphier_cache_disable();
}
u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
-int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point)
+s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
+ u32 context_id)
{
u32 cpu = cpuid & 0xff;
debug_puth(cpuid);
debug_puts(", entry_point=");
debug_puth(entry_point);
+ debug_puts(", context_id=");
+ debug_puth(context_id);
debug_puts("\n");
- psci_save_target_pc(cpu, entry_point);
+ psci_save(cpu, entry_point, context_id);
/* We assume D-cache is off, so do not call flush_dcache() here */
uniphier_psci_holding_pen_release = cpu;
return PSCI_RET_SUCCESS;
}
-void __secure psci_system_reset(u32 function_id)
+void __secure psci_system_reset(void)
{
reset_cpu(0);
}