Merge branch 'master' of http://git.denx.de/u-boot-mmc

[oweals/u-boot.git] / arch / arm / mach-uniphier / arm32 / lowlevel_init.S

diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
index cc34116baaeb2a5c984c309b2cff634bdca1d463..af5ed1c050fe610691521bdddc583169c608c266 100644 (file)
--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -9,8 +11,6 @@
 #include <linux/sizes.h>
 #include <asm/system.h>
 
-#include "ssc-regs.h"
-
 ENTRY(lowlevel_init)
        mov     r8, lr                  @ persevere link reg across call
 
@@ -25,10 +25,6 @@ ENTRY(lowlevel_init)
        orr     r0, r0, #(CR_C | CR_M)  @ enable MMU and Dcache
        mcr     p15, 0, r0, c1, c0, 0
 
-#ifdef CONFIG_DEBUG_LL
-       bl      debug_ll_init
-#endif
-
        bl      setup_init_ram          @ RAM area for stack and page table
 
        /*
@@ -47,6 +43,10 @@ ENTRY(lowlevel_init)
 
        bl      enable_mmu
 
+#ifdef CONFIG_DEBUG_LL
+       bl      debug_ll_init
+#endif
+
        mov     lr, r8                  @ restore link
        mov     pc, lr                  @ back to my caller
 ENDPROC(lowlevel_init)
@@ -86,39 +86,42 @@ ENDPROC(enable_mmu)
  */
 #define BOOT_RAM_SIZE  (SZ_32K)
 #define BOOT_RAM_BASE  ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
-#define BOOT_WAY_BITS  (0x00000100)   /* way 8 */
+#define BOOT_RAM_WAYS  (0x00000100)    @ way 8
+
+#define SSCO_BASE              0x506c0000
+#define SSCOPE                 0x244
+#define SSCOQM                 0x248
+#define SSCOQAD                        0x24c
+#define SSCOQSZ                        0x250
+#define SSCOQWN                        0x258
+#define SSCOPPQSEF             0x25c
+#define SSCOLPQS               0x260
 
 ENTRY(setup_init_ram)
-       /*
-        * Touch to zero for the boot way
-        */
-0:
-       /*
-        * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
-        */
-       ldr     r0, = 0x00408006        @ touch to zero with address range
-       ldr     r1, = SSCOQM
-       str     r0, [r1]
+       ldr     r1, = SSCO_BASE
+       mrc     p15, 0, r0, c2, c0, 0   @ TTBR0
+       ldr     r0, [r0, #0x400]        @ entry for virtual address 0x100*****
+       bfc     r0, #0, #20
+       cmp     r0, #0x50000000         @ is sLD3 page table?
+       biceq   r1, r1, #0xc0000000     @ sLD3 ROM maps 0x5******* to 0x1*******
+
+       /* Touch to zero for the boot way */
+0:     ldr     r0, = 0x00408006        @ touch to zero with address range
+       str     r0, [r1, #SSCOQM]
        ldr     r0, = BOOT_RAM_BASE
-       ldr     r1, = SSCOQAD
-       str     r0, [r1]
+       str     r0, [r1, #SSCOQAD]
        ldr     r0, = BOOT_RAM_SIZE
-       ldr     r1, = SSCOQSZ
-       str     r0, [r1]
-       ldr     r0, = BOOT_WAY_BITS
-       ldr     r1, = SSCOQWN
-       str     r0, [r1]
-       ldr     r1, = SSCOPPQSEF
-       ldr     r0, [r1]
+       str     r0, [r1, #SSCOQSZ]
+       ldr     r0, = BOOT_RAM_WAYS
+       str     r0, [r1, #SSCOQWN]
+       ldr     r0, [r1, #SSCOPPQSEF]
        cmp     r0, #0                  @ check if the command is successfully set
        bne     0b                      @ try again if an error occurs
 
-       ldr     r1, = SSCOLPQS
-1:
-       ldr     r0, [r1]
+1:     ldr     r0, [r1, #SSCOLPQS]
        cmp     r0, #0x4
        bne     1b                      @ wait until the operation is completed
-       str     r0, [r1]                @ clear the complete notification flag
+       str     r0, [r1, #SSCOLPQS]     @ clear the complete notification flag
 
        mov     pc, lr
 ENDPROC(setup_init_ram)