orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
-#ifdef CONFIG_DEBUG_LL
- bl debug_ll_init
-#endif
-
bl setup_init_ram @ RAM area for stack and page table
/*
bl enable_mmu
+#ifdef CONFIG_DEBUG_LL
+ bl debug_ll_init
+#endif
+
mov lr, r8 @ restore link
mov pc, lr @ back to my caller
ENDPROC(lowlevel_init)
ENTRY(setup_init_ram)
ldr r1, = SSCO_BASE
+ mrc p15, 0, r0, c2, c0, 0 @ TTBR0
+ ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
+ bfc r0, #0, #20
+ cmp r0, #0x50000000 @ is sLD3 page table?
+ biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
/* Touch to zero for the boot way */
0: ldr r0, = 0x00408006 @ touch to zero with address range