Merge branch 'master' of http://git.denx.de/u-boot-mmc

[oweals/u-boot.git] / arch / arm / mach-uniphier / arm32 / cache-uniphier.c

diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
index 77a0b78ab443a4c2103ea78d3bbd3a0f6885e10e..658969b049118aa7f958d0b384bc7b65cb046bab 100644 (file)
--- a/arch/arm/mach-uniphier/arm32/cache-uniphier.c
+++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
@@ -72,7 +72,8 @@
 #define UNIPHIER_SSCOQAD_IS_NEEDED(op) \
                ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
 #define UNIPHIER_SSCOQWM_IS_NEEDED(op) \
-               ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY)
+               (((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_WAY) || \
+                ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY))
 
 /* uniphier_cache_sync - perform a sync point for a particular cache level */
 static void uniphier_cache_sync(void)
@@ -184,6 +185,33 @@ void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways)
                                   UNIPHIER_SSCOQM_CM_TOUCH_ZERO);
 }
 
+void uniphier_cache_inv_way(u32 ways)
+{
+       uniphier_cache_maint_common(0, 0, ways,
+                                   UNIPHIER_SSCOQM_S_WAY |
+                                   UNIPHIER_SSCOQM_CM_INV);
+}
+
+void uniphier_cache_set_active_ways(int cpu, u32 active_ways)
+{
+       void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
+
+       switch (readl(UNIPHIER_SSCID)) { /* revision */
+       case 0x11:      /* sLD3 */
+               base = (void __iomem *)UNIPHIER_SSCC + 0x870;
+               break;
+       case 0x12:      /* LD4 */
+       case 0x16:      /* sld8 */
+               base = (void __iomem *)UNIPHIER_SSCC + 0x840;
+               break;
+       default:
+               base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
+               break;
+       }
+
+       writel(active_ways, base + 4 * cpu);
+}
+
 static void uniphier_cache_endisable(int enable)
 {
        u32 tmp;
@@ -206,7 +234,7 @@ void uniphier_cache_disable(void)
        uniphier_cache_endisable(0);
 }
 
-#ifdef CONFIG_UNIPHIER_L2CACHE_ON
+#ifdef CONFIG_CACHE_UNIPHIER
 void v7_outer_cache_flush_all(void)
 {
        uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
@@ -252,7 +280,7 @@ void v7_outer_cache_inval_range(u32 start, u32 end)
 
 void v7_outer_cache_enable(void)
 {
-       writel(U32_MAX, UNIPHIER_SSCLPDAWCR);   /* activate all ways */
+       uniphier_cache_set_active_ways(0, U32_MAX);     /* activate all ways */
        uniphier_cache_enable();
 }