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Merge git://git.denx.de/u-boot-fsl-qoriq
[oweals/u-boot.git] / arch / arm / mach-tegra / tegra210 / xusb-padctl.c
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index 5033543440673edbb2a23f9a5bb994c681e3e60a..a3e3e378e18079390ca7df6030477047ec5155f0 100644 (file)
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -8,6 +8,8 @@
 
 #include <common.h>
 #include <errno.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
 
 #include "../xusb-padctl-common.h"
 
@@ -15,6 +17,78 @@
 
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+enum tegra210_function {
+       TEGRA210_FUNC_SNPS,
+       TEGRA210_FUNC_XUSB,
+       TEGRA210_FUNC_UART,
+       TEGRA210_FUNC_PCIE_X1,
+       TEGRA210_FUNC_PCIE_X4,
+       TEGRA210_FUNC_USB3,
+       TEGRA210_FUNC_SATA,
+       TEGRA210_FUNC_RSVD,
+};
+
+static const char *const tegra210_functions[] = {
+       "snps",
+       "xusb",
+       "uart",
+       "pcie-x1",
+       "pcie-x4",
+       "usb3",
+       "sata",
+       "rsvd",
+};
+
+static const unsigned int tegra210_otg_functions[] = {
+       TEGRA210_FUNC_SNPS,
+       TEGRA210_FUNC_XUSB,
+       TEGRA210_FUNC_UART,
+       TEGRA210_FUNC_RSVD,
+};
+
+static const unsigned int tegra210_usb_functions[] = {
+       TEGRA210_FUNC_SNPS,
+       TEGRA210_FUNC_XUSB,
+};
+
+static const unsigned int tegra210_pci_functions[] = {
+       TEGRA210_FUNC_PCIE_X1,
+       TEGRA210_FUNC_USB3,
+       TEGRA210_FUNC_SATA,
+       TEGRA210_FUNC_PCIE_X4,
+};
+
+#define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)    \
+       {                                                               \
+               .name = _name,                                          \
+               .offset = _offset,                                      \
+               .shift = _shift,                                        \
+               .mask = _mask,                                          \
+               .iddq = _iddq,                                          \
+               .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \
+               .funcs = tegra210_##_funcs##_functions,                 \
+       }
+
+static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
+       TEGRA210_LANE("otg-0",     0x004,  0, 0x3, 0, otg),
+       TEGRA210_LANE("otg-1",     0x004,  2, 0x3, 0, otg),
+       TEGRA210_LANE("otg-2",     0x004,  4, 0x3, 0, otg),
+       TEGRA210_LANE("otg-3",     0x004,  6, 0x3, 0, otg),
+       TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
+       TEGRA210_LANE("hsic-0",    0x004, 14, 0x1, 0, usb),
+       TEGRA210_LANE("hsic-1",    0x004, 15, 0x1, 0, usb),
+       TEGRA210_LANE("pcie-0",    0x028, 12, 0x3, 1, pci),
+       TEGRA210_LANE("pcie-1",    0x028, 14, 0x3, 2, pci),
+       TEGRA210_LANE("pcie-2",    0x028, 16, 0x3, 3, pci),
+       TEGRA210_LANE("pcie-3",    0x028, 18, 0x3, 4, pci),
+       TEGRA210_LANE("pcie-4",    0x028, 20, 0x3, 5, pci),
+       TEGRA210_LANE("pcie-5",    0x028, 22, 0x3, 6, pci),
+       TEGRA210_LANE("pcie-6",    0x028, 24, 0x3, 7, pci),
+       TEGRA210_LANE("sata-0",    0x028, 30, 0x3, 8, pci),
+};
+
 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
@@ -51,7 +125,7 @@ static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
        u32 value;
 
        if (padctl->enable == 0) {
-               error("unbalanced enable/disable");
+               pr_err("unbalanced enable/disable");
                return 0;
        }
 
@@ -209,7 +283,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
                        break;
        }
-
+       if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
@@ -225,7 +302,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
                        break;
        }
-
+       if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
@@ -240,7 +320,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
                        break;
        }
-
+       if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@@ -256,7 +339,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
                        break;
        }
-
+       if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@@ -271,7 +357,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
                        break;
        }
-
+       if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@@ -328,25 +417,41 @@ static struct tegra_xusb_phy tegra210_phys[] = {
 };
 
 static const struct tegra_xusb_padctl_soc tegra210_socdata = {
-       .lanes = NULL,
-       .num_lanes = 0,
-       .functions = NULL,
-       .num_functions = 0,
+       .lanes = tegra210_lanes,
+       .num_lanes = ARRAY_SIZE(tegra210_lanes),
+       .functions = tegra210_functions,
+       .num_functions = ARRAY_SIZE(tegra210_functions),
        .phys = tegra210_phys,
        .num_phys = ARRAY_SIZE(tegra210_phys),
 };
 
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
 {
-       int count, nodes[1];
-
-       debug("> %s(fdt=%p)\n", __func__, fdt);
-
-       count = fdtdec_find_aliases_for_id(fdt, "padctl",
-                                          COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
-                                          nodes, ARRAY_SIZE(nodes));
-       if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata))
-               return;
+       ofnode nodes[1];
+       int count = 0;
+       int ret;
+
+       debug("%s: start\n", __func__);
+       if (of_live_active()) {
+               struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                               "nvidia,tegra210-xusb-padctl");
+
+               debug("np=%p\n", np);
+               if (np) {
+                       nodes[0] = np_to_ofnode(np);
+                       count = 1;
+               }
+       } else {
+               int node_offsets[1];
+               int i;
+
+               count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+                               COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+                               node_offsets, ARRAY_SIZE(node_offsets));
+               for (i = 0; i < count; i++)
+                       nodes[i] = offset_to_ofnode(node_offsets[i]);
+       }
 
-       debug("< %s()\n", __func__);
+       ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
+       debug("%s: done, ret=%d\n", __func__, ret);
 }
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