ARM: tegra: pinmux: add note re: drive group field defines

[oweals/u-boot.git] / arch / arm / mach-tegra / pinmux-common.c

diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
index 6e3ab0c14ca2b477451d1b8b0bd7004938daff00..0bef6e246357c0d929f4297e2d914f5557d822c1 100644 (file)
--- a/arch/arm/mach-tegra/pinmux-common.c
+++ b/arch/arm/mach-tegra/pinmux-common.c
@@ -94,11 +94,15 @@
 void pinmux_set_tristate_input_clamping(void)
 {
        u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
-       u32 val;
 
-       val = readl(reg);
-       val |= CLAMP_INPUTS_WHEN_TRISTATED;
-       writel(val, reg);
+       setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
+}
+
+void pinmux_clear_tristate_input_clamping(void)
+{
+       u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
+
+       clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
 }
 #endif
 
@@ -343,6 +347,21 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 #define SCHMT_SHIFT    3
 #define LPMD_SHIFT     4
 #define LPMD_MASK      (3 << LPMD_SHIFT)
+/*
+ * Note that the following DRV* and SLW* defines are accurate for many drive
+ * groups on many SoCs. We really need a per-group data structure to solve
+ * this, since the fields are in different positions/sizes in different
+ * registers (for different groups).
+ *
+ * On Tegra30/114/124, the DRV*_SHIFT values vary.
+ * On Tegra30, the SLW*_SHIFT values vary.
+ * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
+ *   below are wide enough to cover the widest fields, and hopefully don't
+ *   interfere with any other fields.
+ * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
+ *   wide enough to cover all cases, since that would cause the field to
+ *   overlap with other fields in the narrower cases.
+ */
 #define DRVDN_SHIFT    12
 #define DRVDN_MASK     (0x7F << DRVDN_SHIFT)
 #define DRVUP_SHIFT    20