ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3

[oweals/u-boot.git] / arch / arm / mach-tegra / ivc.c

diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c
index cf6626fb12c7d60983ca8600d9d7e865c8a123f9..65b1cfc07d4e72e1ff53fc528bbdeb4313faf336 100644 (file)
--- a/arch/arm/mach-tegra/ivc.c
+++ b/arch/arm/mach-tegra/ivc.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
  */
 
 #include <common.h>
@@ -493,7 +492,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
               (TEGRA_IVC_ALIGN - 1));
 
        if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) {
-               error("tegra_ivc: nframes * frame_size overflows\n");
+               pr_err("tegra_ivc: nframes * frame_size overflows\n");
                return -EINVAL;
        }
 
@@ -503,12 +502,12 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
         */
        if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) ||
            (qbase2 & (TEGRA_IVC_ALIGN - 1))) {
-               error("tegra_ivc: channel start not aligned\n");
+               pr_err("tegra_ivc: channel start not aligned\n");
                return -EINVAL;
        }
 
        if (frame_size & (TEGRA_IVC_ALIGN - 1)) {
-               error("tegra_ivc: frame size not adequately aligned\n");
+               pr_err("tegra_ivc: frame size not adequately aligned\n");
                return -EINVAL;
        }
 
@@ -521,7 +520,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
        }
 
        if (ret) {
-               error("tegra_ivc: queue regions overlap\n");
+               pr_err("tegra_ivc: queue regions overlap\n");
                return ret;
        }