Merge branch 'master' of git://git.denx.de/u-boot-spi

[oweals/u-boot.git] / arch / arm / mach-tegra / clock.c

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index bac42119cdc52a7bda81a8c550f093b80c528f47..e539ad8b30a7bbe532e267cd2eb0679252e04a0c 100644 (file)
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,12 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0
+ * Copyright (c) 2010-2019, NVIDIA CORPORATION.  All rights reserved.
  */
 
 /* Tegra SoC common clock control functions */
 
 #include <common.h>
+#include <div64.h>
+#include <dm.h>
 #include <errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -15,8 +16,6 @@
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
 
 /*
  * This is our record of the current clock rate of each clock. We don't
@@ -478,6 +477,7 @@ unsigned clock_start_periph_pll(enum periph_id periph_id,
 
        reset_set_enable(periph_id, 1);
        clock_enable(periph_id);
+       udelay(2);
 
        effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
                                                 NULL);
@@ -655,14 +655,13 @@ void clock_ll_start_uart(enum periph_id periph_id)
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-int clock_decode_periph_id(const void *blob, int node)
+int clock_decode_periph_id(struct udevice *dev)
 {
        enum periph_id id;
        u32 cell[2];
        int err;
 
-       err = fdtdec_get_int_array(blob, node, "clocks", cell,
-                                  ARRAY_SIZE(cell));
+       err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
        if (err)
                return -1;
        id = clk_id_to_periph_id(cell[1]);
@@ -816,11 +815,16 @@ void tegra30_set_up_pllp(void)
 
 int clock_external_output(int clk_id)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+       u32 val;
 
        if (clk_id >= 1 && clk_id <= 3) {
-               setbits_le32(&pmc->pmc_clk_out_cntrl,
-                            1 << (2 + (clk_id - 1) * 8));
+               val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
+                                     pmc_clk_out_cntrl));
+               val |= 1 << (2 + (clk_id - 1) * 8);
+               tegra_pmc_writel(val,
+                                offsetof(struct pmc_ctlr,
+                                pmc_clk_out_cntrl));
+
        } else {
                printf("%s: Unknown output clock id %d\n", __func__, clk_id);
                return -EINVAL;