+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
+#include <efi_loader.h>
#include <errno.h>
#include <ns16550.h>
#include <usb.h>
#ifdef CONFIG_TEGRA_CLOCK_SCALING
#include <asm/arch/emc.h>
#endif
-#include <power/as3722.h>
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
-#ifdef CONFIG_PMIC_AS3722
- err = as3722_init(NULL);
- if (err && err != -ENODEV)
- return err;
-#endif
#endif /* CONFIG_SYS_I2C_TEGRA */
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_nand();
#endif
- tegra_xusb_padctl_init(gd->fdt_blob);
+ tegra_xusb_padctl_init();
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
int board_late_init(void)
{
+#if CONFIG_IS_ENABLED(EFI_LOADER)
+ if (gd->bd->bi_dram[1].start) {
+ /*
+ * Only bank 0 is below board_get_usable_ram_top(), so all of
+ * bank 1 is not mapped by the U-Boot MMU configuration, and so
+ * we must prevent EFI from using it.
+ */
+ efi_add_memory_map(gd->bd->bi_dram[1].start,
+ gd->bd->bi_dram[1].size >> EFI_PAGE_SHIFT,
+ EFI_BOOT_SERVICES_DATA, false);
+ }
+#endif
+
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (tegra_cpu_is_non_secure()) {
printf("CPU is in NS mode\n");
- setenv("cpu_ns_mode", "1");
+ env_set("cpu_ns_mode", "1");
} else {
- setenv("cpu_ns_mode", "");
+ env_set("cpu_ns_mode", "");
}
#endif
start_cpu_fan();
{
#ifdef CONFIG_ARM64
return SZ_512M;
+#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
+ // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
+ // from BASE to 4GB, not BASE to BASE+SIZE.
+ return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
#else
return 0;
#endif