+// SPDX-License-Identifier: GPL-2.0+
/*
-* (C) Copyright 2010-2014
-* NVIDIA Corporation <www.nvidia.com>
-*
- * SPDX-License-Identifier: GPL-2.0+
-*/
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
/* Tegra AP (Application Processor) code */
#include <common.h>
+#include <linux/bug.h>
#include <asm/io.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/mc.h>
return TEGRA_SOC_T124;
}
break;
+ case CHIPID_TEGRA210:
+ switch (sku_id) {
+ case SKU_ID_T210_ENG:
+ default:
+ return TEGRA_SOC_T210;
+ }
+ break;
}
/* unknown chip/sku id */
return TEGRA_SOC_UNKNOWN;
}
+#ifndef CONFIG_ARM64
static void enable_scu(void)
{
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
* on BCTs for currently supported SoCs, which are locked down.
* If this changes in new chips, we can revisit this algorithm.
*/
-
- u32 bct_start, odmdata;
+ unsigned long bct_start;
+ u32 odmdata;
bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
int i;
/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
- for (i = 0; i < 23; i++)
- writel(0, &pmc->pmc_scratch1+i);
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+ if (!tegra_cpu_is_non_secure())
+#endif
+ {
+ for (i = 0; i < 23; i++)
+ writel(0, &pmc->pmc_scratch1 + i);
+ }
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
odmdata = get_odmdata();
}
#endif
+#if defined(CONFIG_ARMV7_NONSEC)
+static void smmu_flush(struct mc_ctlr *mc)
+{
+ (void)readl(&mc->mc_smmu_config);
+}
+
+static void smmu_enable(void)
+{
+ struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+ u32 value;
+
+ /*
+ * Enable translation for all clients since access to this register
+ * is restricted to TrustZone-secured requestors. The kernel will use
+ * the per-SWGROUP enable bits to enable or disable translations.
+ */
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
+
+ /*
+ * Enable SMMU globally since access to this register is restricted
+ * to TrustZone-secured requestors.
+ */
+ value = readl(&mc->mc_smmu_config);
+ value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
+ writel(value, &mc->mc_smmu_config);
+
+ smmu_flush(mc);
+}
+#else
+static void smmu_enable(void)
+{
+}
+#endif
+
void s_init(void)
{
/* Init PMC scratch memory */
/* init the cache */
config_cache();
- /* init vpr */
- config_vpr();
+ /* enable SMMU */
+ smmu_enable();
}
+#endif