Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dm

[oweals/u-boot.git] / arch / arm / mach-sunxi / clock_sun6i.c

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 9068c88ab2f8548877258969f5055c8162764562..1628f3a7b6d3f67af89ea2751ac8d242c15b9e0a 100644 (file)
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * sun6i specific clock code
  *
@@ -6,8 +7,6 @@
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -35,7 +34,7 @@ void clock_init_safe(void)
        clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
 #endif
 
-#ifdef CONFIG_MACH_SUN8I_R40
+#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
        /* Set PLL lock enable bits and switch to old lock mode */
        writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
 #endif
@@ -51,6 +50,13 @@ void clock_init_safe(void)
        writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
        if (IS_ENABLED(CONFIG_MACH_SUN6I))
                writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+
+#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
+       setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
+       setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
+       setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
+       setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
+#endif
 }
 #endif
 
@@ -59,11 +65,17 @@ void clock_init_sec(void)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       struct sunxi_prcm_reg * const prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
        setbits_le32(&ccm->ccu_sec_switch,
                     CCM_SEC_SWITCH_MBUS_NONSEC |
                     CCM_SEC_SWITCH_BUS_NONSEC |
                     CCM_SEC_SWITCH_PLL_NONSEC);
+       setbits_le32(&prcm->prcm_sec_switch,
+                    PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
+                    PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
+                    PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
 #endif
 }
 
@@ -137,7 +149,11 @@ void clock_set_pll3(unsigned int clk)
 {
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifdef CONFIG_SUNXI_DE2
+       const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
+#else
        const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+#endif
 
        if (clk == 0) {
                clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
@@ -150,6 +166,22 @@ void clock_set_pll3(unsigned int clk)
               &ccm->pll3_cfg);
 }
 
+#ifdef CONFIG_SUNXI_DE2
+void clock_set_pll3_factors(int m, int n)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       /* PLL3 rate = 24000000 * n / m */
+       writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+              CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
+              &ccm->pll3_cfg);
+
+       while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
+               ;
+}
+#endif
+
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 {
        struct sunxi_ccm_reg * const ccm =
@@ -222,6 +254,28 @@ done:
 }
 #endif
 
+#ifdef CONFIG_SUNXI_DE2
+void clock_set_pll10(unsigned int clk)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       const int m = 2; /* 12 MHz steps */
+
+       if (clk == 0) {
+               clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
+               return;
+       }
+
+       /* PLL10 rate = 24000000 * n / m */
+       writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
+              CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
+              &ccm->pll10_cfg);
+
+       while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
+               ;
+}
+#endif
+
 #if defined(CONFIG_MACH_SUN8I_A33) || \
     defined(CONFIG_MACH_SUN8I_R40) || \
     defined(CONFIG_MACH_SUN50I)