Merge branch '2019-05-28-master-imports'

[oweals/u-boot.git] / arch / arm / mach-sunxi / board.c

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 4507279cc55fc1129e3bc91d017e81740dade9ba..8e9bb63d9d2fc85d1ad2202f214470d13df0cfd5 100644 (file)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  *
@@ -6,17 +7,13 @@
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * Some init for sunxi platform.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <mmc.h>
 #include <i2c.h>
 #include <serial.h>
-#ifdef CONFIG_SPL_BUILD
 #include <spl.h>
-#endif
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -55,7 +52,7 @@ static struct mm_region sunxi_mem_map[] = {
                /* RAM */
                .virt = 0x40000000UL,
                .phys = 0x40000000UL,
-               .size = 0x80000000UL,
+               .size = 0xC0000000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
                         PTE_BLOCK_INNER_SHARE
        }, {
@@ -110,6 +107,10 @@ static int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
        sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
+       sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
+       sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
+       sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
@@ -204,17 +205,16 @@ void s_init(void)
        clock_init();
        timer_init();
        gpio_init();
+#ifndef CONFIG_DM_I2C
        i2c_init_board();
+#endif
        eth_init_board();
 }
 
-#ifdef CONFIG_SPL_BUILD
-DECLARE_GLOBAL_DATA_PTR;
-
 /* The sunxi internal brom will try to loader external bootloader
  * from mmc0, nand flash, mmc2.
  */
-u32 spl_boot_device(void)
+uint32_t sunxi_get_boot_device(void)
 {
        int boot_source;
 
@@ -240,10 +240,12 @@ u32 spl_boot_device(void)
        boot_source = readb(SPL_ADDR + 0x28);
        switch (boot_source) {
        case SUNXI_BOOTED_FROM_MMC0:
+       case SUNXI_BOOTED_FROM_MMC0_HIGH:
                return BOOT_DEVICE_MMC1;
        case SUNXI_BOOTED_FROM_NAND:
                return BOOT_DEVICE_NAND;
        case SUNXI_BOOTED_FROM_MMC2:
+       case SUNXI_BOOTED_FROM_MMC2_HIGH:
                return BOOT_DEVICE_MMC2;
        case SUNXI_BOOTED_FROM_SPI:
                return BOOT_DEVICE_SPI;
@@ -253,10 +255,10 @@ u32 spl_boot_device(void)
        return -1;              /* Never reached */
 }
 
-/* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(const u32 boot_device)
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_device(void)
 {
-       return MMCSD_MODE_RAW;
+       return sunxi_get_boot_device();
 }
 
 void board_init_f(ulong dummy)
@@ -286,10 +288,15 @@ void reset_cpu(ulong addr)
                /* sun5i sometimes gets stuck without this */
                writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
        }
-#elif defined(CONFIG_SUNXI_GEN_SUN6I)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
+#if defined(CONFIG_MACH_SUN50I_H6)
+       /* WDOG is broken for some H6 rev. use the R_WDOG instead */
        static const struct sunxi_wdog *wdog =
-                ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
+               (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
+#else
+       static const struct sunxi_wdog *wdog =
+               ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+#endif
        /* Set the watchdog for its shortest interval (.5s) and wait */
        writel(WDT_CFG_RESET, &wdog->cfg);
        writel(WDT_MODE_EN, &wdog->mode);
@@ -298,7 +305,7 @@ void reset_cpu(ulong addr)
 #endif
 }
 
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */